Crystal-to-HSTL, 100MHz/ 200MHz
PCI Express™ Clock Synthesizer
842S104E
Datasheet
General Description
The 842S104E is a PLL-based clock generator specifically designed
for PCI Express™ Clock Generation 2 applications. This device
generates either a 200MHz or 100MHz differential HSTL clock from
an input reference of 25MHz. The input reference may be derived
from an external source or by the addition of a 25MHz crystal to the
on-chip crystal oscillator. An external reference is applied to the
XTAL_IN pin with the XTAL_OUT pin left floating.The device offers
spread spectrum clock output for reduced EMI applications. An I
2
C
bus interface is used to enable or disable spread spectrum operation
as well as select either a down spread value of -0.35% or -0.5%.The
842S104E is available in a lead-free 24-Lead package.
Features
•
•
•
•
•
•
•
•
•
•
•
Four differential HSTL output pairs
Crystal oscillator interface: 25MHz
Output frequency: 100MHz or 200MHz
RMS phase jitter @ 200MHz (12kHz – 20MHz): 1.229ps (typical)
Cycle-to-cycle jitter: 25ps (maximum)
I
2
C support with readback capabilities up to 400kHz
Spread Spectrum for electromagnetic interference (EMI) reduction
3.3V core/1.5V to 2.0V output operating supply
0°C to 70°C ambient operating temperature
Available lead-free (RoHS 6) package
PCI Express Gen2 Jitter Compliant
HiPerClockS™
Block Diagram
XTAL_IN
XTAL_OUT
SDATA
SCLK
Pullup
Pullup
25MHz
Pin Assignment
PLL
Divider
Network
4
4
SRCT[1:4]
SRCC[1:4]
OSC
I
2
C
Logic
SRCT3
SRCC3
V
SS
V
DDO
SRCT2
SRCC2
SRCT1
SRCC1
V
SS
V
DD
V
SS
nc
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SRCC4
SRCT4
V
DDO
SDATA
SCLK
XTAL_OUT
XTAL_IN
V
DD
V
SS
nc
V
DDA
V
SS
842S104E
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
©2016 Integrated Device Technology, Inc
1
January 4, 2016
842S104E Datasheet
Pin Description and Pin Characteristics Tables
Table 1. Pin Descriptions
Number
1, 2
3, 9,
11, 13, 16
4, 22
5, 6
7, 8
10, 17
12, 15
14
18, 19
20
21
23, 24
Name
SRCT3, SRCC3
V
SS
V
DDO
SRCT2, SRCC2
SRCT1, SRCC1
V
DD
nc
V
DDA
XTAL_IN, XTAL_OUT
SCLK
SDATA
SRCT4, SRCC4
Type
Output
Power
Power
Output
Output
Power
Unused
Power
Input
Input
I/O
Output
Pullup
Pullup
Description
Differential output pair. HSTL interface levels.
Power supply ground.
Output power supply pins.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Core supply pins.
No connect.
Analog supply for PLL.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
I
2
C compatible SCLK. This pin has an internal pullup resistor.
LVCMOS/LVTTL interface levels.
I
2
C compatible SDATA. This pin has an internal pullup resistor. Open drain.
LVCMOS/LVTTL interface levels.
Differential output pair. HSTL interface levels.
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
Maximum
Units
pF
k
©2016 Integrated Device Technology, Inc
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January 4, 2016
842S104E Datasheet
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a
two-signal I
2
C serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock output
buffers, can be individually enabled or disabled. The registers
associated with the serial interface initialize to their default setting
upon power-up, therefore, use of this interface is optional. Clock
device register changes are normally made upon system
initialization, if any are required.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block
write and block read operations from the controller. For block
write/read operation, the bytes must be accessed in sequential
order from lowest to highest byte (most significant bit first) with the
ability to stop after any complete byte has been transferred. For
byte write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed byte is
encoded in the command code, as described in Table 3A.
The block write and block read protocol is outlined in Table 3B,
while Table 3C outlines the corresponding byte write and byte read
protocol. The slave receiver address is 11010010 (D2h).
Table 3A.Command Code Definition
Bit
7
6:5
4:0
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation.
Chip select address, set to “00” to access device.
Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be “00000”.
Table 3B. Block Read and Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
Description = Block Write
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Byte Count - 8 bits
Acknowledge from slave
Data byte 1 - 8 bits
Acknowledge from slave
Data byte 2 - 8 bits
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N - 8 bits
Acknowledge from slave
Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
Description = Block Read
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave - 8 bits
Acknowledge
Data Byte 1 from slave - 8 bits
Acknowledge
Data Byte 2 from slave - 8 bits
Acknowledge
Data Bytes from Slave/Acknowledge
Data Byte N from slave - 8 bits
Not Acknowledge
©2016 Integrated Device Technology, Inc
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January 4, 2016
842S104E Datasheet
Table 3C. Byte Read and Byte Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29
Description = Byte Write
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Data Byte - 8 bits
Acknowledge from slave
Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39
Description = Byte Read
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read
Acknowledge from slave
Data from slave - 8 bits
Not Acknowledge
Stop
©2016 Integrated Device Technology, Inc
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January 4, 2016
842S104E Datasheet
Control Registers
Table 3D. Byte 0: Control Register 0
Bit
7
6
@Pup
0
1
Name
Reserved
SRC[T/C]4
Description
Reserved
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z)
1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z)
1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z)
1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z)
1 = Enable
Reserved
Reserved
Reserved
Table 3F. Byte 2: Control Register 2
Bit
7
6
5
4
3
@Pup
1
1
1
0
1
Name
SRCT/C
Reserved
Reserved
Reserved
Reserved
Description
Spread Spectrum Selection
0 = -0.35%, 1 = -0.5%
Reserved
Reserved
Reserved
Reserved
SRC Spread Spectrum
Enable
0 = Spread Off,
1 = Spread On
Reserved
Output Frequency Control
0 = 100MHz
1 = 200MHz
5
1
SRC[T/C]3
4
1
SRC[T/C]2
2
0
SRC
3
2
1
0
1
1
0
0
SRC[T/C]1
Reserved
Reserved
Reserved
1
0
1
1
Reserved
FOUTCTL
NOTE: @PUP denotes at power-up.
Table 3E. Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 3G. Byte 3:Control Register 3
Bit
7
6
5
4
3
2
1
0
@Pup
1
0
1
0
1
1
1
1
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
©2016 Integrated Device Technology, Inc
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January 4, 2016
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