M54HC137
RAD-HARD 3 TO 8 LINE DECODER/LATCH (INVERTING)
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
t
PD
=18ns (TYP.) at V
CC
= 6V
LOW POWER DISSIPATION:
I
CC
= 2µA (MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 137
SPACE GRADE-1: ESA SCC QUALIFIED
50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
DEVICE FULLY COMPLIANT WITH
SCC-9205-013
DILC-16
FPC-16
ORDER CODES
PACKAGE
DILC
FPC
FM
M54HC137D
M54HC137K
EM
M54HC137D1
M54HC137K1
DESCRIPTION
The M54HC137 is an high speed CMOS 3 TO 8
LINE DECODER/LATCH (INVERTING) fabricated
with silicon gate C
2
MOS technology.
This device is a 3 to 8 line decoder with latches on
the three address inputs. When GL goes from low
to high, the addresses present at the select inputs
(A, B, and C) is stored in the latches. As long as
GL remains high no address changes will be
recognized. Output enable pins G1 and G2,
control the state of the outputs independently of
the select or latch-enable inputs. All the outputs
are high unless G1 is high and G2 is low. The
54HC137 is ideally suited for the implementation
of glitch-free decoders in stored-address
application in bus oriented systems.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION
March 2004
1/10
M54HC137
IEC LOGIC SYMBOLS
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN N°
1, 2, 3
4
5
6
9, 10, 11, 12,
13, 14, 15,
7
8
16
SYMBOL
A to C
GL
G2
G1
Y0 to Y7
NAME AND FUNCTION
Data Inputs
Latch Enable Input (Active
LOW)
Data Enable Input (Active
LOW)
Data Enable Input (Active
HIGH)
Multiplexer Outputs
GND
V
CC
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUTS
ENABLE
GL
X
X
L
L
L
L
L
L
L
L
H
G1
X
L
H
H
H
H
H
H
H
H
H
G2
H
X
L
L
L
L
L
L
L
L
L
C
X
X
L
L
L
L
H
H
H
H
X
SELECT
B
X
X
L
L
H
H
L
L
H
H
X
A
X
X
L
H
L
H
L
H
L
H
X
Y0
H
H
L
H
H
H
H
H
H
H
Y1
Y2
Y3
Y4
Y5
Y6
Y7
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
Outputs corresponding to stored address L: all others H
2/10
M54HC137
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6ns)
Test Condition
Symbol
Parameter
V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
T
A
= 25°C
Min.
Typ.
30
8
7
45
14
12
50
15
13
70
22
19
70
21
18
12
3
3
8
2
2
Max.
75
15
13
115
23
20
115
23
20
170
34
29
165
33
28
50
10
9
50
10
9
5
5
5
Value
-40 to 85°C
Min.
Max.
95
19
16
145
29
25
145
29
25
215
43
37
205
41
35
65
13
11
60
12
10
5
5
5
-55 to 125°C
Min.
Max.
110
22
19
175
35
30
175
35
30
250
50
43
110
22
19
75
15
13
75
15
13
5
5
5
ns
Unit
t
TLH
t
THL
Output Transition
Time
t
PLH
t
PHL
Propagation Delay
Time (G1 - Yn)
t
PLH
t
PHL
Propagation Delay
Time (G2 - Yn)
t
PLH
t
PHL
Propagation Delay
Time (GL - Yn)
t
PLH
t
PHL
Propagation Delay
Time (A, B, C - Y)
t
W(H)
t
W(L)
t
s
Minimum Pulse
Width (GL)
Minimum Set-up
Time (A, B, C - GL)
Minimum Hold
Time (A, B, C - GL)
ns
ns
ns
ns
ns
ns
t
h
ns
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
V
CC
(V)
5.0
5.0
T
A
= 25°C
Min.
Typ.
5
55
Max.
10
Value
-40 to 85°C
Min.
Max.
10
-55 to 125°C
Min.
Max.
10
pF
pF
Unit
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance (note
1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
5/10
Embedded System
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