0
®
XC1700D Family of
Serial Configuration PROMs
0
5*
November 25, 1997 (Version 1.1)
Product Specification
Features
• Extended family of one-time programmable (OTP)
bit-serial read-only memories used for storing the
configuration bitstreams of Xilinx FPGAs
• On-chip address counter, incremented by each rising
edge on the clock input
• Simple interface to the FPGA requires only one user
I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active Low)
for compatibility with different FPGA solutions
• XC17128D or XC17256D supports XC4000 fast
configuration mode (12.5 MHz)
• Low-power CMOS EPROM process
• Available in 5 V and 3.3 V versions
• Available in plastic and ceramic packages, and
commercial, industrial and military temperature ranges
• Space efficient 8-pin DIP, 8-pin SOIC, 8-pin VOIC, or
20-pin surface-mount packages.
• Programming support by leading programmer
manufacturers.
V
CC
V
PP
GND
Description
The XC1700 family of serial configuration PROMs (SCPs)
provides an easy-to-use, cost-effective method for storing
Xilinx FPGA configuration bitstreams.
When the FPGA is in master serial mode, it generates a
configuration clock that drives the SCP. A short access time
after the rising clock edge, data appears on the SCP DATA
output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
SCP. When the FPGA is in slave mode, the SCP and the
FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all SCPs in this chain
are interconnected. All devices are compatible and can be
cascaded with other members of the family.
For device programming, the XACT development system
compiles the FPGA design file into a standard Hex format,
which is then transferred to the programmer.
CE
RESET/
OE or
OE/
RESET
CLK
Address Counter
TC
CEO
EPROM
Cell
Matrix
Output
OE
DATA
X3185
Figure 1: Simplified Block Diagram (does not show programming circuit)
November 25, 1997 (Version 1.1)
5-11
XC1700D Family of Serial Configuration PROMs
Pin Description
DATA
Data output, 3-stated when either CE or OE are inactive.
During programming, the DATA pin is I/O. Note that OE can
be programmed to be either active High or active Low.
Serial PROM Pinouts
Pin Name
DATA
CLK
RESET/OE (OE/RESET)
CE
GND
CEO
V
PP
V
CC
8-Pin
1
2
3
4
5
6
7
8
20-Pin
2
4
6
8
10
14
17
20
CLK
Each rising edge on the CLK input increments the internal
address counter, if both CE and OE are active.
RESET/OE
When High, this input holds the address counter reset and
3-states the DATA output. The polarity of this input pin is
programmable as either RESET/OE or OE/RESET. To
avoid confusion, this document describes the pin as
RESET/OE, although the opposite polarity is possible on all
devices. When RESET is active, the address counter is
held at zero, and the DATA output is 3-stated. The polarity
of this input is programmable. The default is active High
RESET, but the preferred option is active Low RESET,
because it can be driven by the FPGA’s INIT pin.
The polarity of this pin is controlled in the programmer inter-
face. This input pin is easily inverted using the Xilinx HW-
130 programmer software. Third-party programmers have
different methods to invert this pin.
Capacity
Device
XC1718D or L
XC1736D
XC1765D or L
XC17128D or L
XC17256D or L
XC17512L
XC1701 or L
Configuration Bits
18,144
36,288
65,536
131,072
262,144
524,288
1,048,576
CE
When High, this pin disables the internal address counter,
3-states the DATA output, and forces the device into low-I
CC
standby mode.
CEO
Chip Enable output, to be connected to the CE input of the
next SCP in the daisy chain. This output is Low when the
CE and OE inputs are both active AND the internal address
counter has been incremented beyond its Terminal Count
(TC) value. In other words: when the PROM has been read,
CEO will follow CE as long as OE is active. When OE goes
inactive, CEO stays High until the PROM is reset. Note that
OE can be programmed to be either active High or active
Low.
V
PP
Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read oper-
ation, this pin
must
be connected to V
CC
. Failure to do so
may lead to unpredictable, temperature-dependent opera-
tion and severe problems in circuit debugging.
Do not leave
VPP floating!
V
CC
and GND
V
CC
is positive supply pin and GND is ground pin.
5-12
November 25, 1997 (Version 1.1)
Number of Configuration Bits, Including Header
for all Xilinx FPGAs and Compatible SCP Type
Device
XC3x20A/L
XC3x30A/L
XC3x42A/L
XC3x64A/L
XC3x90A/L
XC3195A
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028EX/XL
XC4036EX/XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
XC5202
XC5204
XC5206
XC5210
XC5215
Configuration Bits
14,819
22,216
30,824
46,104
64,200
94,984
53,984
95,008
119,840
147,552
178,144
247,968
329,312
422,176
151,960
283,424
393,623
521,880
668,184
832,528
1,014,928
1,215,368
1,433,864
1,924,992
42,416
70,704
106,288
165,488
237,744
SCP
XC1718D
XC1736D
XC1736D
XC1765D
XC1765D
XC17128D
XC1765D
XC17128D/L
XC17128D
XC17256D
XC17256D/L
XC17256D/L
XC1701
XC1701
XC17256L
XC17512L
XC17512L
XC17512L
XC1701L
XC1701L
XC1701L
XC1701L +
XC17256L
XC1701L +
XC17512L
2 XC1701L
XC1765D
XC17128D
XC17128D
XC17256D
XC17256D
in step with the FPGA’s internal power-on-reset, which
may not be a safe assumption.
• The CE input of the lead (or only) Serial PROM is driven
by the DONE/PRGM or DONE output of the lead FPGA
device, provided that DONE/PRGM is not permanently
grounded. Otherwise, LDC can be used to drive CE, but
must then be unconditionally High during user
operation. CE can also be permanently tied Low, but
this keeps the DATA output active and causes an
unnecessary supply current of 10 mA maximum.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Logic Cell Array and their
associated interconnections are established by a configu-
ration program. The program is loaded either automatically
upon power up, or on command, depending on the state of
the three FPGA mode pins. In Master Mode, the FPGA
automatically loads the configuration program from an
external memory. The Serial Configuration PROM has
been designed for compatibility with the Master Serial
Mode.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial Mode whenever all three of the FPGA mode-
select pins are Low (M0=0, M1=0, M2=0). Data is read from
the Serial Configuration PROM sequentially on a single
data line. Synchronization is provided by the rising edge of
the temporary signal CCLK, which is generated during con-
figuration.
Master Serial Mode provides a simple configuration inter-
face. Only a serial data line and two control lines are
required to configure an FPGA. Data from the Serial Con-
figuration PROM is read sequentially, accessed via the
internal address and bit counters which are incremented on
every valid rising edge of CCLK.
If the user-programmable, dual-function DIN pin on the
FPGA is used only for configuration, it must still be held at
a defined level during normal operation. The XC3000 and
XC4000 families take care of this automatically with an on-
chip default pull-up resistor. With XC2000-family devices,
the user must either configure DIN as an active output, or
provide a defined level, e.g., by using an external pull-up
resistor, if DIN is configured as an input.
Controlling Serial PROMs
Most connections between the FPGA device and the Serial
PROM are simple and self-explanatory.
The DATA output(s) of the of the Serial PROM(s) drives
the DIN input of the lead FPGA device.
• The master FPGA CCLK output drives the CLK input(s)
of the Serial PROM(s).
• The CEO output of a Serial PROM drives the CE input
of the next Serial PROM in a daisy chain (if any).
• The RESET/OE input of all Serial PROMs is best driven
by the INIT output of the XC3000 or XC4000 lead
FPGA device. This connection assures that the Serial
PROM address counter is reset before the start of any
(re)configuration, even when a reconfiguration is
initiated by a V
CC
glitch. Other methods – such as
driving RESET/OE from LDC or system reset – assume
that the Serial PROM internal power-on-reset is always
•
Programming the FPGA With Counters
Unchanged Upon Completion
When multiple FPGA-configurations for a single FPGA are
stored in a Serial Configuration PROM, the OE pin should
be tied Low. Upon power-up, the internal address counters
are reset and configuration begins with the first program
stored in memory. Since the OE pin is held Low, the
address counters are left unchanged after configuration is
complete. Therefore, to reprogram the FPGA with another
program, the D/P line is pulled Low and configuration
begins at the last value of the address counters.
November 25, 1997 (Version 1.1)
5-13
XC1700D Family of Serial Configuration PROMs
This method fails if a user applies RESET during the FPGA
configuration process. The FPGA aborts the configuration
and then restarts a new configuration, as intended, but the
Serial PROM does not reset its address counter, since it
never saw a High level on its OE input. The new configura-
tion, therefore, reads the remaining data in the PROM and
interprets it as preamble, length count etc. Since the FPGA
is the master, it issues the necessary number of CCLK
pulses, up to 16 million (2
24
) and D/P goes High. However,
the FPGA configuration will be completely wrong, with
potential contentions inside the FPGA and on its output
pins. This method must, therefore, never be used when
there is any chance of external reset during configuration.
caded SCPs provide additional memory. After the last bit
from the first SCP is read, the next clock signal to the SCP
asserts its CEO output Low and disables its DATA line. The
second SCP recognizes the Low level on its CE input and
enables its DATA output. See
Figure 2.
After configuration is complete, the address counters of all
cascaded SCPs are reset if the FPGA RESET pin goes
Low, assuming the SCP reset polarity option has been
inverted.
To reprogram the FPGA with another program, the D/P line
goes Low and configuration begins where the address
counters had stopped. In this case, avoid contention
between DATA and the configured I/O use of DIN.
Cascading Serial Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
5-14
November 25, 1997 (Version 1.1)
*
If Readback is
Activated, a
5-kΩ Resistor is
Required in
Series With M1
During Configuration
the 5 kΩ M2 Pull-Down
Resistor Overcomes the
Internal Pull-Up,
but it Allows M2 to
be User I/O.
General-
Purpose
User I/O
Pins
•
•
•
•
•
*
M0
DOUT
M2
HDC
LDC
INIT
+5 V
M1 PWRDWN
OPTIONAL
Daisy-chained
FPGAs with
Different
Configurations
Other
I/O Pins
XC3000
FPGA
Device
OPTIONAL
Slave FPGAs
with Identical
Configurations
+5 V
RESET
RESET
DIN
CCLK
D/P
INIT
V
CC
DATA
CLK
SCP
CE
OE/RESET
CEO
CE
V
PP
DATA
CLK
Cascaded
Serial
Memory
OE/RESET
(Low Resets the Address Pointer)
CCLK
(OUTPUT)
DIN
DOUT
(OUTPUT)
X5090
Figure 2: Master Serial Mode.
The one-time-programmable Serial Configuration PROM supports automatic loading of
configuration programs. Multiple devices can be cascaded to support additional FPGA. An early D/P inhibits the
PROM data output one CCLK cycle before the FPGA I/Os become active.
November 25, 1997 (Version 1.1)
5-15
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