ACTS280K datasheet, PDF - EEWORLD Datasheet

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ACTS280K: DescriptionACT SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDFP14; Categorylogic logic; File Size57KB，4 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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ACTS280K Overview

ACT SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDFP14

ACTS280K Parametric

Parameter Name	Attribute value
package instruction	,
Reach Compliance Code	unknown
Other features	ODD/EVEN PARITY GENERATOR
series	ACT
JESD-30 code	R-CDFP-F14
Logic integrated circuit type	PARITY GENERATOR/CHECKER
Number of digits	9
Number of functions	1
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	CERAMIC, METAL-SEALED COFIRED
Package shape	RECTANGULAR
Package form	FLATPACK
Certification status	Not Qualified
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	FLAT
Terminal location	DUAL
Base Number Matches	1

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ACTS280MS

January 1996

Radiation Hardened 9-Bit Odd/

Even Parity Generator Checker

Pinouts

14 PIN CERAMIC DUAL-IN-LINE

MIL-STD-1835 DESIGNATOR, CDIP2-T14,

LEAD FINISH C

TOP VIEW

I6 1

I7 2

NC 3

I8 4

EVEN 5

ODD 6

GND 7

14 VCC

13 I5

12 I4

11 I3

10 I2

9 I1

8 I0

Features

• Devices QML Qualiﬁed in Accordance with MIL-PRF-38535

• Detailed Electrical and Screening Requirements are Contained in

SMD# 5962-96720 and Intersil’ QM Plan

• 1.25 Micron Radiation Hardened SOS CMOS

• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)

• Single Event Upset (SEU) Immunity: <1 x 10

-10

Errors/Bit/Day

(Typ)

• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm

/mg

• Dose Rate Upset . . . . . . . . . . . . . . . . >10

RAD (Si)/s, 20ns Pulse

• Dose Rate Survivability . . . . . . . . . . . >10

RAD (Si)/s, 20ns Pulse

• Latch-Up Free Under Any Conditions

• Military Temperature Range . . . . . . . . . . . . . . . . . . -55

C to +125

• Signiﬁcant Power Reduction Compared to ALSTTL Logic

• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V

• Input Logic Levels

- VIL = 0.8V Max

- VIH = VCC/2 Min

• Input Current

≤

1µA at VOL, VOH

• Fast Propagation Delay . . . . . . . . . . . . . . . . 24ns (Max), 16ns (Typ)

14 PIN CERAMIC FLATPACK

MIL-STD-1835 DESIGNATOR, CDFP3-F14

LEAD FINISH C

TOP VIEW

EVEN

ODD

GND

VCC

Description

The Intersil ACTS280MS is a Radiation Hardened 9-bit odd/even parity

generator checker device. Both odd and even parity outputs are available

for generating or checking parity for words up to 9 bits long. Even parity

is indicated (EVEN output high) when an even number of data inputs are

high. Odd parity is indicated (ODD output high) when an odd number of

data inputs are high. Parity checking for larger words can be accom-

plished by tying EVEN output to any input of an additional ACTS280MS.

The ACTS280MS utilizes advanced CMOS/SOS technology to achieve

high-speed operation. This device is a member of a radiation hardened,

high-speed, CMOS/SOS Logic Family.

The ACTS280MS is supplied in a 14 lead Ceramic Flatpack (K sufﬁx) or

a Ceramic Dual-In-Line Package (D sufﬁx).

Ordering Information

PART NUMBER

5962F9672001VCC

5962F9672001VXC

ACTS280D/Sample

ACTS280K/Sample

ACTS280HMSR

TEMPERATURE RANGE

-55

C to +125

-55

C to +125

SCREENING LEVEL

MIL-PRF-38535 Class V

Sample

Die

PACKAGE

14 Lead SBDIP

14 Lead Ceramic Flatpack

14 Lead SBDIP

14 Lead Ceramic Flatpack

Die

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Intersil Corporation 1999

Spec Number

File Number

518827

3569.1

ACTS280K Related Products

	ACTS280K	5962F9672001VCC	5962F9672001VXC	ACTS280HMSR
Description	ACT SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDFP14	ACT SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDIP14	ACT SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDFP14	ACT SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, UUC13
package instruction	,	DIP, DIP14,.3	DFP, FL14,.3	DIE,
Reach Compliance Code	unknown	not_compliant	not_compliant	unknown
series	ACT	ACT	ACT	ACT
JESD-30 code	R-CDFP-F14	R-CDIP-T14	R-CDFP-F14	S-XUUC-N16
Logic integrated circuit type	PARITY GENERATOR/CHECKER	PARITY GENERATOR/CHECKER	PARITY GENERATOR/CHECKER	PARITY GENERATOR/CHECKER
Number of digits	9	9	9	9
Number of functions	1	1	1	1
Number of terminals	14	14	14	16
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	UNSPECIFIED
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	SQUARE
Package form	FLATPACK	IN-LINE	FLATPACK	UNCASED CHIP
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V
surface mount	YES	NO	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Terminal form	FLAT	THROUGH-HOLE	FLAT	NO LEAD
Terminal location	DUAL	DUAL	DUAL	UPPER
Maximum operating temperature	125 °C	125 °C	125 °C	-
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-
Temperature level	MILITARY	MILITARY	MILITARY	-
Base Number Matches	1	1	1	-
Parts packaging code	-	DIP	DFP	DIE
Contacts	-	14	14	16
encapsulated code	-	DIP	DFP	DIE
propagation delay (tpd)	-	24 ns	24 ns	24 ns
Filter level	-	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V
total dose	-	300k Rad(Si) V	300k Rad(Si) V	300k Rad(Si) V

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