ACS08MS
July 1998
Radiation Hardened
Quad 2-Input AND Gate
Description
The Radiation Hardened ACS08MS is a Quad 2-Input AND
Gate. For each gate, a HIGH level on both the A and B
inputs results in a HIGH level on the Y output. A LOW level
on either the A or B input results in a LOW level on the Y
output. All inputs are buffered and the outputs are designed
for balanced propagation delay and transition times.
The ACS08MS is fabricated on a CMOS Silicon on
Sapphire (SOS) process, which provides an immunity to
Single Event Latch-up and the capability of highly reliable
performance in any radiation environment. These devices
offer significant power reduction and faster performance
when compared to ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACS08 are
contained in SMD 5962-95651. A “hot-link” is provided
on our homepage with instructions for downloading.
www.intersil.com/data/sm/index.asp
Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25Micron Radiation Hardened SOS CMOS
• Radiation Environment
- Latch-up Free Under any Conditions
- Total Dose . . . . . . . . . . . . . . . . . . . . . . 3 x 10
5
RAD(Si)
- SEU Immunity . . . . . . . . . . . <1 x 10
-10
Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . >100MeV/(mg/cm
2
)
• Input Logic Levels . . .V
IL
= (0.3)(V
CC
), V
IH
= (0.7)(V
CC
)
• Output Current . . . . . . . . . . . . . . . . . . . . . . .
±8mA
(Min)
• Quiescent Supply Current. . . . . . . . . . . . . 100µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . .15ns (Max)
Applications
• High Speed Control Circuits
• Sensor Monitoring
• Low Power Designs
Ordering Information
ORDERING NUMBER
5962F9565101VCC
ACS08D/SAMPLE
5962F9565101VXC
ACS08K/SAMPLE
5962F9565101V9A
INTERNAL MARKETING NUMBER
ACS08DMSR
ACS08D/SAMPLE
ACS08KMSR
ACS08K/SAMPLE
ACS08HMSR
TEMP. RANGE (
o
C)
-55 to 125
25
-55 to 125
25
25
PACKAGE
14 Ld SBDIP
14 Ld SBDIP
14 Ld Flatpack
14 Ld Flatpack
Die
DESIGNATOR
CDIP2-T14
CDIP2-T14
CDFP4-F14
CDFP4-F14
N/A
Pinouts
ACS08 (SBDIP)
TOP VIEW
A1 1
B1 2
Y1 3
A2 4
B2 5
Y2 6
GND 7
14 V
CC
13 B4
12 A4
11 Y4
10 B3
9 A3
8 Y3
ACS08 (FLATPACK)
TOP VIEW
A1
B1
Y1
A2
B2
Y2
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
B4
A4
Y4
B3
A3
Y3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3993.1
1
ACS08MS
Die Characteristics
DIE DIMENSIONS:
Size: 2390µm x 2390µm (94 mils x 94 mils)
Thickness: 525µm
±25µm
(20.6 mils
±1
mil)
Bond Pad: 110µm x 110µm (4.3 mils x 4.3 mils)
METALLIZATION:
Al
Metal 1 Thickness: 0.7µm
±0.1µm
Metal 2 Thickness: 1.0µm
±0.1µm
SUBSTRATE POTENTIAL:
Unbiased Insulator
PASSIVATION
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30µm
±0.15µm
SPECIAL INSTRUCTIONS:
Bond V
CC
First
ADDITIONAL INFORMATION:
Worst Case Density: <2.0 x 10
5
A/cm
2
Transistor Count: 176
Metallization Mask Layout
ACS08MS
B1
A1
V
CC
B4
Y1
A4
A2
Y4
NC
NC
B2
B3
Y2
GND
Y3
A3
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Sales Office Headquarters
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Intersil Corporation
P. O. Box 883, Mail Stop 53-204
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2
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