Revision 7
SmartFusion Customizable System-on-Chip (cSoC)
Microcontroller Subsystem (MSS)
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Hard 100 MHz 32-Bit ARM
®
Cortex™-M3
– 1.25 DMIPS/MHz Throughput from Zero Wait State
Memory
– Memory Protection Unit (MPU)
– Single Cycle Multiplication, Hardware Divide
– JTAG Debug (4 wires), Serial Wire Debug (SWD, 2
wires), and Single Wire Viewer (SWV) Interfaces
Internal Memory
– Embedded Nonvolatile Flash Memory (eNVM), 128
Kbytes to 512 Kbytes
– Embedded High-Speed SRAM (eSRAM), 16 Kbytes
to 64 Kbytes, Implemented in 2 Physical Blocks to
Enable Simultaneous Access from 2 Different
Masters
Multi-Layer AHB Communications Matrix
– Provides up to 16 Gbps of On-Chip Memory
Bandwidth,
1
Allowing Multi-Master Schemes
10/100 Ethernet MAC with RMII Interface
2
Programmable External Memory Controller, Which
Supports:
– Asynchronous Memories
– NOR Flash, SRAM, PSRAM
– Synchronous SRAMs
Two I
2
C Peripherals
Two 16550 Compatible UARTs
Two SPI Peripherals
Two 32-Bit Timers
32-Bit Watchdog Timer
8-Channel DMA Controller to Offload the Cortex-M3
from Data Transactions
Clock Sources
– 32 KHz to 20 MHz Main Oscillator
– Battery-Backed 32 KHz Low Power Oscillator with
Real-Time Counter (RTC)
– 100 MHz Embedded RC Oscillator; 1% Accurate
– Embedded Analog PLL with 4 Output Phases (0, 90,
180, 270)
Based on proven ProASIC
®
3 FPGA Fabric
Low Power, Firm-Error Immune 130-nm, 7-Layer Metal,
Flash-Based CMOS Process
Nonvolatile, Live at Power-Up, Retains Program When
Powered Off
350 MHz System Performance
Embedded SRAMs and FIFOs
– Variable Aspect Ratio 4,608-Bit SRAM Blocks
– x1, x2, x4, x9, and x18 Organizations
– True Dual-Port SRAM (excluding x18)
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– Programmable Embedded FIFO Control Logic
Secure ISP with 128-Bit AES via JTAG
FlashLock
®
to Secure FPGA Contents
Five Clock Conditioning Circuits (CCCs) with up to 2
Integrated Analog PLLs
– Phase Shift, Multiply/Divide, and Delay Capabilities
– Frequency: Input 1.5–350 MHz, Output 0.75 to
350 MHz
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Programmable Analog
Analog Front-End (AFE)
•
Up to Three 12-Bit SAR ADCs
– 500 Ksps in 12-Bit Mode
– 550 Ksps in 10-Bit Mode
– 600 Ksps in 8-Bit Mode
Internal 2.56 V Reference or Optional External
Reference
One First-Order
ΣΔ
DAC (sigma-delta) per ADC
– 12-Bit 500 Ksps Update Rate
Up to 5 High-Performance Analog Signal Conditioning
Blocks (SCB) per Device, Each Including:
– Two High-Voltage Bipolar Voltage Monitors (with 4
input ranges from ±2.5 V to –11.5/+14 V) with 1%
Accuracy
– High Gain Current Monitor, Differential Gain = 50, up
to 14 V Common Mode
– Temperature Monitor (Resolution = ¼°C in 12-Bit
Mode; Accurate from –55°C to 150°C)
Up to Ten High-Speed Voltage Comparators
(t
pd
= 15 ns)
Offloads Cortex-M3–Based MSS from Analog
Initialization and Processing of ADC, DAC, and SCBs
Sample Sequence Engine for ADC and DAC Parameter
Set-Up
Post-Processing Engine for Functions such as Low-
Pass Filtering and Linear Transformation
Easily Configured via GUI in Libero
®
Integrated Design
(IDE) Software
FPGA I/Os
– LVDS, PCI, PCI-X, up to 24 mA IOH/IOL
– Up to 350 MHz
MSS I/Os
– Schmitt Trigger, up to 6 mA IOH, 8 mA IOL
– Up to 180 MHz
Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
External 1.5 V Is Allowed by Bypassing Regulator
(digital VCC = 1.5 V for FPGA and MSS, analog VCC =
3.3 V and 1.5 V)
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Analog Compute Engine (ACE)
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High-Performance FPGA
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I/Os and Operating Voltage
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1 Theoretical maximum
2 A2F200 and larger devices
August 2011
© 2011 Microsemi Corporation
I
SmartFusion Customizable System-on-Chip (cSoC)
SmartFusion cSoC Family Product Table
SmartFusion cSoC
FPGA Fabric
System Gates
Tiles (D-flip-flops)
RAM Blocks (4,608 bits)
Microcontroller
Subsystem (MSS)
Flash (Kbytes)
SRAM (Kbytes)
Cortex-M3 with memory protection unit (MPU)
10/100 Ethernet MAC
External Memory Controller (EMC)
DMA
I
2
C
SPI
16550 UART
32-Bit Timer
PLL
32 KHz Low Power Oscillator
100 MHz On-Chip RC Oscillator
Main Oscillator (32 KHz to 20 MHz)
Programmable
Analog
ADCs (8-/10-/12-bit SAR)
DACs (12-bit sigma-delta)
Signal Conditioning Blocks (SCBs)
Comparator
3
Current Monitors
3
Temperature Monitors
3
Bipolar High Voltage Monitors
3
1
1
1
2
1
1
2
1
1
1
1
2
2
4
8
4
4
8
3
4
3
4
5
4
10
4
5
4
5
4
10
4
No
8 Ch
2
2
2
2
1
2
2
A2F060
60,000
1,536
8
128
16
Yes
Yes
24-bit address,16-bit data
1
A2F200
200,000
4,608
8
256
64
A2F500
500,000
11,520
24
512
64
Notes:
1. Not available on A2F500 for the PQ208 package.
2. Two PLLs are available in CS288 and FG484 (one PLL in FG256 and PQ208).
3. These functions share I/O pins and may not all be available at the same time. See the "Analog Front-End Overview" section in
the
SmartFusion Programmable Analog User’s Guide
for details.
4. Available on FG484 only. PQ208, FG256, and CS288 packages offer the same programmable analog capabilities as A2F200.
II
R ev i si o n 7
SmartFusion Customizable System-on-Chip (cSoC)
Package I/Os: MSS + FPGA I/Os
Device
Package
Direct Analog Inputs
Shared Analog Inputs
1
Total Analog Inputs
Total Analog Outputs
MSS I/Os
2,3
FPGA I/Os
Total I/Os
A2F060
CS288
11
4
15
1
28
4
68
112
FG256
11
4
15
1
26
4
66
108
PQ208
8
16
24
1
22
66
113
A2F200
CS288
8
16
24
2
31
78
135
FG256
8
16
24
2
25
66
117
FG484
8
16
24
2
41
94
161
PQ208
8
16
24
1
22
66
113
A2F500
CS288
8
16
24
2
31
78
135
FG256
8
16
24
2
25
66
117
FG484
12
20
32
3
41
128
5
204
Notes:
1. These pins are shared between direct analog inputs to the ADCs and voltage/current/temperature monitors.
2. 16 MSS I/Os are multiplexed and can be used as FPGA I/Os, if not needed for MSS. These I/Os support Schmitt triggers and
support only LVTTL and LVCMOS (1.5 / 1.8 / 2.5, 3.3 V) standards.
3. 9 MSS I/Os are primarily for 10/100 Ethernet MAC and are also multiplexed and can be used as FPGA I/Os if Ethernet MAC is
not used in a design. These I/Os support Schmitt triggers and support only LVTTL and LVCMOS (1.5 / 1.8 / 2.5, 3.3 V
standards.
4. 10/100 Ethernet MAC is not available on A2F060.
5. EMC is not available on the A2F500 PQ208 package.
SmartFusion cSoC Device Status
Device
A2F060
A2F200
A2F500
Status
Preliminary: CS288, FG256
Production: FG256, FG484, PQ208
Preliminary: CS288
Production: FG256, FG484, PQ208
Preliminary: CS288
Revision 7
III
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