A54SX32AFBG256 datasheet, PDF - EEWORLD Datasheet

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A54SX32AFBG256: DescriptionField Programmable Gate Array, 2880 CLBs, 32000 Gates, 240MHz, CMOS, PBGA256, 1 MM PITCH, PLASTIC, FBGA-256; CategoryProgrammable logic devices Programmable logic; File Size784KB，45 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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A54SX32AFBG256 Overview

Field Programmable Gate Array, 2880 CLBs, 32000 Gates, 240MHz, CMOS, PBGA256, 1 MM PITCH, PLASTIC, FBGA-256

A54SX32AFBG256 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Objectid	1822046254
package instruction	LBGA,
Reach Compliance Code	compliant
Other features	ALSO REQUIRES 5V FOR I/O SUPPLY
maximum clock frequency	240 MHz
Combined latency of CLB-Max	1.3 ns
JESD-30 code	S-PBGA-B256
length	17 mm
Humidity sensitivity level	3
Configurable number of logic blocks	2880
Equivalent number of gates	32000
Number of terminals	256
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2880 CLBS, 32000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.68 mm
Maximum supply voltage	2.7 V
Minimum supply voltage	2.3 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	17 mm

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A d van ced v.1

54SXA Family FPGAs

Specifications

Output Tristate at Powerup

• 100% Resource Utilization with 100% Pin Locking

• 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with

5.0V Input Tolerance

• Very Low Power Consumption

• Deterministic, User-Controllable Timing

• Unique In-System Diagnostic and Debug capability

with Silicon Explorer

• JTAG Boundary Scan Testing in Compliance with

IEEE Standard 1149.1

• Actel Designer Series Design Tools, Supported by

Cadence, Exemplar, IST, Mentor Graphics, Model

Tech, Synopsys, Synplicity, and Viewlogic Design

Entry and Simulation Tools

• Secure Programming Technology Prevents Reverse

Engineering and Design Theft

• 8,000 to 72,000 Available Logic Gates

• Up to 360 User-Programmable I/O Pins

• 4,024 Flip-Flops

• 0.25 Micro CMOS

Features

• I/Os with Live, or “Hot,” Insertion/Removal Capability

• Power Up/Down Friendly (No Sequencing Required

for Supply Voltage)

• 66 MHz PCI

• CPLD and FPGA Integration

• Single Chip Solution

• Configurable I/Os to Support Varity of I/O Standards,

Such as 3.3V PCI, LVTTL, TTL, and 5V PCI.

• Configurable Weak Resistor Pullup or Pulldown for

SX Pr odu ct Prof ile

A54SX08A

Gate Capacity

Logic Modules

Combinatorial Cells

Maximum Flip-Flops

User I/Os (Maximum)

Clocks

Quadrant Clocks

JTAG

PCI

Clock-to-Out

Input Set-Up (External)

Speed Grades

Temperature Grades

Packages (by pin count)

PQFP

TQFP

PBGA

8,000

768

512

256

512

130

Yes

TBD

Std, –1, –2, –3

C, I, M

208

100, 144

144

A54SX16A

16,000

1,452

924

528

990

177

Yes

TBD

Std, –1, –2, –3

C, I, M

208

100, 144

144

A54SX32A

32,000

2,880

1,800

1,080

1,980

249

Yes

4.5 ns

-1.3 ns

Std, –1, –2, –3

C, I, M

208

144

144, 256, 329

A54SX72A

72,000

6,036

4,024

2,012

4,024

360

Yes

4.8 ns

-3.3 ns

Std, –1, –2, –3

C, I, M

208

—

484

Apr il 1 9 9 9

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