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A54SX16A-1FBGG144

Description
Field Programmable Gate Array, 1452 CLBs, 16000 Gates, CMOS, PBGA144, 1 MM PITCH, PLASTIC, FBGA-144
CategoryProgrammable logic devices    Programmable logic   
File Size784KB,45 Pages
ManufacturerActel
Websitehttp://www.actel.com/
Environmental Compliance
Download Datasheet Parametric View All

A54SX16A-1FBGG144 Overview

Field Programmable Gate Array, 1452 CLBs, 16000 Gates, CMOS, PBGA144, 1 MM PITCH, PLASTIC, FBGA-144

A54SX16A-1FBGG144 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
package instruction1 MM PITCH, PLASTIC, FBGA-144
Reach Compliance Codecompliant
Other featuresALSO REQUIRES 5V FOR I/O SUPPLY
JESD-30 codeS-PBGA-B144
JESD-609 codee1
length13 mm
Humidity sensitivity level3
Configurable number of logic blocks1452
Equivalent number of gates16000
Number of terminals144
Maximum operating temperature70 °C
Minimum operating temperature
organize1452 CLBS, 16000 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeLBGA
Package shapeSQUARE
Package formGRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)260
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height1.55 mm
Maximum supply voltage2.7 V
Minimum supply voltage2.3 V
Nominal supply voltage2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN SILVER COPPER
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature40
width13 mm
Base Number Matches1
A d van ced v.1
54SXA Family FPGAs
Specifications
Output Tristate at Powerup
• 100% Resource Utilization with 100% Pin Locking
• 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with
5.0V Input Tolerance
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Debug capability
with Silicon Explorer
• JTAG Boundary Scan Testing in Compliance with
IEEE Standard 1149.1
• Actel Designer Series Design Tools, Supported by
Cadence, Exemplar, IST, Mentor Graphics, Model
Tech, Synopsys, Synplicity, and Viewlogic Design
Entry and Simulation Tools
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
• 8,000 to 72,000 Available Logic Gates
• Up to 360 User-Programmable I/O Pins
• 4,024 Flip-Flops
• 0.25 Micro CMOS
Features
• I/Os with Live, or “Hot,” Insertion/Removal Capability
• Power Up/Down Friendly (No Sequencing Required
for Supply Voltage)
• 66 MHz PCI
• CPLD and FPGA Integration
• Single Chip Solution
• Configurable I/Os to Support Varity of I/O Standards,
Such as 3.3V PCI, LVTTL, TTL, and 5V PCI.
• Configurable Weak Resistor Pullup or Pulldown for
SX Pr odu ct Prof ile
A54SX08A
Gate Capacity
Logic Modules
Combinatorial Cells
Register Cells (Dedicated Flip-Flops)
Maximum Flip-Flops
User I/Os (Maximum)
Clocks
Quadrant Clocks
JTAG
PCI
Clock-to-Out
Input Set-Up (External)
Speed Grades
Temperature Grades
Packages (by pin count)
PQFP
TQFP
PBGA
8,000
768
512
256
512
130
3
0
Yes
Yes
TBD
TBD
Std, –1, –2, –3
C, I, M
208
100, 144
144
A54SX16A
16,000
1,452
924
528
990
177
3
0
Yes
Yes
TBD
TBD
Std, –1, –2, –3
C, I, M
208
100, 144
144
A54SX32A
32,000
2,880
1,800
1,080
1,980
249
3
0
Yes
Yes
4.5 ns
-1.3 ns
Std, –1, –2, –3
C, I, M
208
144
144, 256, 329
A54SX72A
72,000
6,036
4,024
2,012
4,024
360
3
4
Yes
Yes
4.8 ns
-3.3 ns
Std, –1, –2, –3
C, I, M
208
484
Apr il 1 9 9 9
1
© 1999 Actel Corporation
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