BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
64K X 16 bit
BS616LV1011
• Wide Vcc operation voltage : 2.4 ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade : 22mA (@55ns) operating current
I- grade : 23mA (@55ns) operating current
C-grade : 17mA (@70ns) operating current
I- grade : 18mA (@70ns) operating current
0.4uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 48mA (55ns) operating current
I- grade : 50mA (55ns) operating current
C-grade : 36mA (70ns) operating current
I- grade : 38mA (70ns) operating current
1.3uA (Typ.) CMOS standby current
• High speed access time :
-55
55ns
-70
70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
DESCRIPTION
The BS616LV1011 is a high performance , very low power CMOS Static
Random Access Memory organized as 65,536 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.4uA at 3V/25
o
C and maximum access time of 55ns at 3V/85
o
C.
Easy memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable(OE) and three-state output drivers.
The BS616LV1011 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV1011 is available in the JEDEC standard 44-pin TSOP
Type II and 48-pin BGA package.
POWER DISSIPATION
STANDBY
Operating
(I
CCSB1
, Max)
(I
CC
, Max)
PRODUCT FAMILY
PRODUCT
FAMILY
BS616LV1011EC
BS616LV1011AC
BS616LV1011EI
BS616LV1011AI
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
(ns)
55ns:2.8~5.5V
70ns:2.5~5.5V
PKG TYPE
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
70ns
Vcc=3.0V
70ns
+0 C to +70 C
O
O
2.4V ~ 5.5V
55/70
4uA
1.3uA
36mA
17mA
TSOP2-44
BGA-48-0608
TSOP2-44
BGA-48-0608
-40 C to +85 C
O
O
2.4V ~ 5.5V
55/70
8uA
2.5uA
38mA
18mA
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
6
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
BLOCK DIAGRAM
A8
A13
A15
A14
A12
A7
A6
A5
A4
Address
Input
Buffer
BS616LV1011EC
BS616LV1011EI
18
Row
Decoder
512
Memory Array
512 x 2048
2048
DQ0
16
Data
Input
Buffer
16
Column I/O
2
3
4
5
A
LB
OE
A0
A1
A2
NC
.
.
.
.
DQ15
.
.
.
.
Write Driver
Sense Amp
128
Column Decoder
16
Data
Output
16
Buffer
B
IO8
UB
A3
A4
CE
IO0
C
IO9
IO10
A5
A6
IO1
IO2
CE
WE
OE
UB
LB
Control
14
Address Input Buffer
D
VSS
IO11
NC
A7
IO3
VCC
E
VCC
IO12
NC
NC
IO4
VSS
A11 A9 A3 A2 A1 A0 A10
F
IO14
IO13
A14
A15
IO5
IO6
Vcc
Gnd
G
IO15
NC
A12
A13
WE
IO7
H
NC
A8
A9
A10
A11
NC
Brilliance Semiconductor, Inc
.
reserves the right to modify document contents without notice.
R0201-BS616LV1011
1
Revision 1.0
Apr.
2004
BSI
PIN DESCRIPTIONS
BS616LV1011
Name
A0-A15 Address Input
CE Chip Enable Input
Function
These 16 address inputs select one of the 65,536 x 16-bit words in the RAM.
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
DQ0 - DQ15 Data Input/Output
Ports
Vcc
Gnd
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
TRUTH TABLE
MODE
Not selected
(Power Down)
Output Disabled
Read
CE
H
L
L
WE
X
H
H
OE
X
H
L
LB
X
X
L
H
L
L
Write
L
L
X
H
L
UB
X
X
L
L
H
L
L
H
DQ0~DQ7
High Z
High Z
Dout
High Z
Dout
Din
X
Din
DQ8~DQ15
High Z
High Z
Dout
Dout
High Z
Din
Din
X
Vcc CURRENT
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
R0201-BS616LV1011
2
Revision 1.0
Apr.
2004
BSI
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
V
cc
T
BIAS
T
STG
P
T
I
OUT
PARAMETER
Terminal Voltage with
Respect to GND
Power Supply Voltage
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
BS616LV1011
OPERATING RANGE
UNITS
V
V
O
RATING
-0.5 to
Vcc+0.5
-0.5 to
Vcc+0.5
-40 to +85
-60 to +150
1.0
20
RANGE
Commercial
Industrial
AMBIENT
TEMPERATURE
0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
2.4V ~ 5.5V
2.4V ~ 5.5V
C
C
O
W
mA
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
C
IN
C
DQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
V
IN
=0V
V
I/O
=0V
6
8
pF
pF
1. This parameter is guaranteed and not 100% tested.
DC ELECTRICAL CHARACTERISTICS
( TA = -40
o
C to + 85
o
C )
PARAMETER
NAME
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
(6)
PARAMETER
Guaranteed Input Low
Voltage
(2)
Guaranteed Input High
Voltage
(3)
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Standby Current-TTL
TEST CONDITIONS
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
MIN.
-0.5
2.0
2.2
--
--
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
TYP.
(1)
--
--
--
--
--
--
--
--
--
--
0.4
1.3
MAX.
0.8
Vcc+0.3
1
1
0.4
--
18
38
1
2
2.5
8
UNITS
V
V
uA
uA
V
V
mA
Vcc = Max, V
IN
= 0V to Vcc
Vcc = Max, CE = V
IH
, or OE = V
IH
,
V
I/O
= 0V to Vcc
Vcc = Max, I
OL
= 2mA
Vcc = Min, I
OH
= -1mA
CE = V
IL
, I
DQ
= 0mA,
F = Fmax
(4)
CE = V
IH
, I
DQ
= 0mA
CE
≧
Vcc-0.2V,
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
70ns
--
2.4
--
--
--
--
--
--
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
I
CCSB
I
CCSB1
(5)
mA
Standby Current-CMOS
uA
1. Typical characteristics are at TA = 25
o
C.
3. Overshoot : Vcc+1.5V in case of pulse width
≦
20ns.
5. I
cc
s
B1_Max.
is 1.3uA/4.0uA at Vcc=3.0V/5.0V and T
A
=70
o
C.
2. Undershoot : -1.5V in case of pulse width
≦
20ns.
4. Fmax = 1/t
RC
.
6. Icc
_Max.
is 23mA(@3V)/ 50mA(@5V) under 55ns operation.
DATA RETENTION CHARACTERISTICS
( TA = -40
o
C to + 85
o
C )
SYMBOL
V
DR
I
CCDR
(3)
PARAMETER
Vcc for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
TEST CONDITIONS
CE
≧
Vcc - 0.2V
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
CE
≧
Vcc - 0.2V
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
See Retention Waveform
MIN.
1.5
--
0
T
RC
(2)
TYP.
(1)
--
0.15
--
--
MAX.
--
0.8
--
--
UNITS
V
uA
ns
ns
t
CDR
t
R
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
O
C.
3. I
cc
DR_MAX.
is 0.45uA at T
A
=70
R0201-BS616LV1011
3
Revision 1.0
Apr.
2004
BSI
LOW V
CC
DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
BS616LV1011
Vcc
V
IH
Vcc
V
DR
≥
1.5V
Vcc
t
CDR
CE
≥
Vcc - 0.2V
t
R
V
IH
CE
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
KEY TO SWITCHING WAVEFORMS
Vcc / 0V
1V/ns
0.5Vcc
C
L
= 30pF+1TTL
C
L
= 100pF+1TTL
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
,
AC ELECTRICAL CHARACTERISTICS
( TA = -40
o
C to + 85
o
C )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
CYCLE TIME : 55ns
CYCLE TIME : 70ns
(Vcc = 2.5~5.5V)
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Data Hold from Address Change
(Vcc = 2.8~5.5V)
MIN. TYP. MAX.
UNIT
MIN. TYP. MAX.
t
AVAX
t
AVQV
t
ELQV
t
BA
t
GLQV
t
E1LQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
t
RC
t
AA
t
ACS
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
(1)
55
--
--
(LB,UB)
--
--
10
(LB,UB)
10
5
--
(LB,UB)
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
25
25
--
--
--
20
20
20
--
70
--
--
--
--
10
10
5
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
35
35
--
--
--
25
25
25
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE :
1. t
BA
is 25ns/35ns (@speed=55ns/70ns) with address toggle. ; t
BA
is 55ns/70ns (@speed=55ns/70ns) without address toggle.
R0201-BS616LV1011
4
Revision 1.0
Apr.
2004
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
BS616LV1011
t
RC
ADDRESS
t
D
OUT
t
OH
AA
t
OH
READ CYCLE2
(1,3,4)
CE
t
ACS
t
BA
LB,UB
t
BE
D
OUT
t
(5)
CLZ
t
BDO
t
(5)
CHZ
READ CYCLE3
(1,4)
t
ADDRESS
RC
t
OE
AA
t
OE
CE
t
OH
t
OLZ
t
(5)
CLZ
t
ACS
t
OHZ
(5)
(1,5)
t
CHZ
t
BA
LB,UB
t
BE
D
OUT
t
BDO
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = V
IL
.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. The parameter is guaranteed but not 100% tested.
R0201-BS616LV1011
5
Revision 1.0
Apr.
2004
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