FX-700-DAE-KNKN-B7-D9 datasheet, PDF

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> FX-700-DAE-KNKN-B7-D9

FX-700-DAE-KNKN-B7-D9: DescriptionConverter,; CategoryWireless rf/communication Telecom circuit; File Size398KB，8 Pages; ManufacturerVectron International, Inc.; Websitehttp://www.vectron.com/; Environmental Compliance

Download Datasheet Parametric View All

FX-700-DAE-KNKN-B7-D9 Overview

Converter,

FX-700-DAE-KNKN-B7-D9 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
package instruction	QCCN, LCC16,.3x.2,40
Reach Compliance Code	compliant
Other features	also works in 5v nominal supply voltage
app	ATM;SDH;SONET
JESD-30 code	R-CQCC-N16
JESD-609 code	e4
length	7.49 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	CERAMIC
encapsulated code	QCCN
Encapsulate equivalent code	LCC16,.3x.2,40
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Maximum seat height	2.13 mm
Maximum slew rate	40 mA
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	ATM/SONET/SDH SUPPORT CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	Gold (Au) - with Nickel (Ni) barrier
Terminal form	NO LEAD
Terminal pitch	1.02 mm
Terminal location	QUAD
width	5.08 mm
Base Number Matches	1

Preview

Download Datasheet

View All

FX-700

Low Jitter Frequency Translator

FX-700

Description

The FX-700 is a crystal-based frequency translator used in communications applications where low jitter is paramount.

Performance advantages include superior jitter performance, high output frequencies and small package size. Advanced custom

ASIC technology results in a highly robust, reliable and predictable device. The device is packaged in a 16 pad ceramic package

with a hermetic seam welded lid.

Features

•

5.0 x 7.5 mm, Hermetically sealed SMD package

Frequency Translation to 77.760 MHz

3.3 Volt or 5.0 Volt Supply

Tri-State Output allows board test

Lock Detect

Commercial or Industrial Temp. Range

CMOS Output

Absolute Pull Range Performance to +/-100 ppm

Capable of locking to an 8 kHz pulse/BITS clock

Product is free of lead and compliant to EC RoHS Directive

•

Applications

Frequency Translation, Clock Smoothing

Telecom - SONET/SDH/ATM

Datacom – DSLAM, DSLAR, Access Nodes

Base Station – GSM, CDMA

Cable Modem Head End

Block Diagram

(8)

C1 Charge

Pump Out

(5)

Charge

Pump

OUT

(3)

(16)

VCXO

OUT

(13)

FIN

(6)

(1-64)

Phase

Detector

& LD

(1-16384)

FOUT

(10)

(1)

(11)

(2)

(14)

VCXO

(12)

TRI-STATE

(4)

GND

(7, 9)

Figure 1. Functional block diagram

Page 1 of 8

Tape and Reel

Table 6. Tape and Reel Information

Tape Dimensions (mm)

7.5

1.5

20.2

Reel Dimensions (mm)

16.4

178

#/Reel

200

Figure 4. Tape and Reel

FX-700 Theory of Operation

The FX-700 includes an integrated phase detector, current mode charge pump, programmable frequency dividers and VCXO. The

FX-700 will translate an input frequency such as 8 kHz, 1.544 MHz or 19.440 MHz to a speciﬁc output frequency which is an integer

multiple (1-16384) of the input frequency and less than or equal to 77.760 MHz. For clock smoothing applications, the input

frequency is typically internally divided down by a factor of 64 (2N where N = 6) by the input frequency divider and this frequency

becomes an input to the phase detector. The integrated frequency dividers (factory programmed) and crystal based VCXO allows

for a large range of possible frequency translations and clock smoothing applications.

The FX-700’s PLL is a feedback system which forces the output frequency to lock in both phase and frequency to the input

frequency. While there will be some phase error, theory states there is no frequency error. The loop ﬁlter design will dictate many

key parameters such as jitter reduction, stability, lock range and acquisition time. The external second order passive loop ﬁlter is

a complex impedance in parallel with the input capacitance of the VCXO. The loop ﬁlter converts the charge pump output into

the VCXO’s control voltage. VI’s loop ﬁlter design methodology involves the calculation of the open loop gain bandwidth and

corresponding phase margin to determine the optimal component values that ensure high loop stability and acceptable lock in

time. As a rule of thumb, the VCXO gain is typically 100 ppm/volt and the charge pump current is typically 32 uA.

VI’s Applications Engineering staﬀ can provide the external loop ﬁlter component values required to meet speciﬁc system

requirements and application.

Suggested FX-700 Circuit Conﬁguration Drawing

Page 5 of 8

Recommended Resources

Battery-driven low-power reference voltage generation circuit

Voltage Controlled ECL (Emitter Coupled Logic) Integrated Circuit Crystal Oscillator Generator Circuit

CMOS-NMOS interface circuit

The most practical basic diagram circuit 48 - one-phase overcurrent protection circuit

Circuit that converts sine wave to square wave

IGBT equivalent circuit with parasitic transistor

The company closed down and all kinds of parts were sold at low prices.: The company has been closed and some items are being transferred. In addition, there are 3 brand new 15-inch LCD screens (industrial screen 4:3), 2 brand new 15-inch touch screens (4:3), and 6 12-inch...; hujaky Buy&Sell

Can the 66AK2L06 SoC enable miniaturization of test and measurement equipment?: All electronic products have their design, development and production processes closely related to their test and measurement equipment? For all electronic products, the purpose of test and measuremen...; Jacktang DSP and ARM Processors

Android transplantation WIFI: [b][size=22pt]1. [/size][/b][b][font=宋体][size=22pt]Preface[/size][/font] [/b][b] [/b][b][size=22pt] [/size][/b] [font=宋体]Hardware platform: [/font] marvel 310 [font=宋体]Software platform: [/font] maemo...; 老夫子 Embedded System

How to Eliminate Latch in ISE VHDL: I wrote a state machine, read and write from RAM 64 times, after integration, it alarmed that the read and write address port has latches (12-bit address, so there are 24 in total). I checked online a...; timdong FPGA/CPLD

Can the Micron 360 camera be connected to a DSP that supports the 656 interface?: I want to use Micron 360 (MT9V011) as the interface of my ipcamera, but dsp only supports 656 interface, and MI360 does not say whether it supports 656 interface. 360 should output digital RGB interfa...; xinqing Embedded System

Help: I urgently need help from a master to find a schematic diagram and program of a school schedule management system made by a 51 single-chip microcomputer....; zhj940927 51mcu

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components