FX-700-DAT-KNKN-B8-D5 datasheet, PDF

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> FX-700-DAT-KNKN-B8-D5

FX-700-DAT-KNKN-B8-D5: DescriptionConverter,; CategoryWireless rf/communication Telecom circuit; File Size398KB，8 Pages; ManufacturerVectron International, Inc.; Websitehttp://www.vectron.com/; Environmental Compliance

Download Datasheet Parametric View All

FX-700-DAT-KNKN-B8-D5 Overview

Converter,

FX-700-DAT-KNKN-B8-D5 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
package instruction	QCCN, LCC16,.3x.2,40
Reach Compliance Code	compliant
Other features	also works in 5v nominal supply voltage
app	ATM;SDH;SONET
JESD-30 code	R-CQCC-N16
JESD-609 code	e4
length	7.49 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC
encapsulated code	QCCN
Encapsulate equivalent code	LCC16,.3x.2,40
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Maximum seat height	2.13 mm
Maximum slew rate	40 mA
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	ATM/SONET/SDH SUPPORT CIRCUIT
Temperature level	COMMERCIAL
Terminal surface	Gold (Au) - with Nickel (Ni) barrier
Terminal form	NO LEAD
Terminal pitch	1.02 mm
Terminal location	QUAD
width	5.08 mm
Base Number Matches	1

Preview

Download Datasheet

View All

FX-700

Low Jitter Frequency Translator

FX-700

Description

The FX-700 is a crystal-based frequency translator used in communications applications where low jitter is paramount.

Performance advantages include superior jitter performance, high output frequencies and small package size. Advanced custom

ASIC technology results in a highly robust, reliable and predictable device. The device is packaged in a 16 pad ceramic package

with a hermetic seam welded lid.

Features

•

5.0 x 7.5 mm, Hermetically sealed SMD package

Frequency Translation to 77.760 MHz

3.3 Volt or 5.0 Volt Supply

Tri-State Output allows board test

Lock Detect

Commercial or Industrial Temp. Range

CMOS Output

Absolute Pull Range Performance to +/-100 ppm

Capable of locking to an 8 kHz pulse/BITS clock

Product is free of lead and compliant to EC RoHS Directive

•

Applications

Frequency Translation, Clock Smoothing

Telecom - SONET/SDH/ATM

Datacom – DSLAM, DSLAR, Access Nodes

Base Station – GSM, CDMA

Cable Modem Head End

Block Diagram

(8)

C1 Charge

Pump Out

(5)

Charge

Pump

OUT

(3)

(16)

VCXO

OUT

(13)

FIN

(6)

(1-64)

Phase

Detector

& LD

(1-16384)

FOUT

(10)

(1)

(11)

(2)

(14)

VCXO

(12)

TRI-STATE

(4)

GND

(7, 9)

Figure 1. Functional block diagram

Page 1 of 8

Tape and Reel

Table 6. Tape and Reel Information

Tape Dimensions (mm)

7.5

1.5

20.2

Reel Dimensions (mm)

16.4

178

#/Reel

200

Figure 4. Tape and Reel

FX-700 Theory of Operation

The FX-700 includes an integrated phase detector, current mode charge pump, programmable frequency dividers and VCXO. The

FX-700 will translate an input frequency such as 8 kHz, 1.544 MHz or 19.440 MHz to a speciﬁc output frequency which is an integer

multiple (1-16384) of the input frequency and less than or equal to 77.760 MHz. For clock smoothing applications, the input

frequency is typically internally divided down by a factor of 64 (2N where N = 6) by the input frequency divider and this frequency

becomes an input to the phase detector. The integrated frequency dividers (factory programmed) and crystal based VCXO allows

for a large range of possible frequency translations and clock smoothing applications.

The FX-700’s PLL is a feedback system which forces the output frequency to lock in both phase and frequency to the input

frequency. While there will be some phase error, theory states there is no frequency error. The loop ﬁlter design will dictate many

key parameters such as jitter reduction, stability, lock range and acquisition time. The external second order passive loop ﬁlter is

a complex impedance in parallel with the input capacitance of the VCXO. The loop ﬁlter converts the charge pump output into

the VCXO’s control voltage. VI’s loop ﬁlter design methodology involves the calculation of the open loop gain bandwidth and

corresponding phase margin to determine the optimal component values that ensure high loop stability and acceptable lock in

time. As a rule of thumb, the VCXO gain is typically 100 ppm/volt and the charge pump current is typically 32 uA.

VI’s Applications Engineering staﬀ can provide the external loop ﬁlter component values required to meet speciﬁc system

requirements and application.

Suggested FX-700 Circuit Conﬁguration Drawing

Page 5 of 8

Recommended Resources

Light control indicator circuit

Class A super power amplifier

Grating circuit diagram of threshold switch

LA3161 power amplifier circuit

Refrigerator automatic deodorizer circuit

Test probe circuit

Studying the Road to Electric Motor Driving-5: Vector Addition and Subtraction: [i=s]This post was last edited by MianQi on 2021-6-16 18:43[/i]Studying the Road to Electric Motor Driving-5: Vector Addition and Subtraction...; MianQi Motor Drive Control（Motor Control）

Push-up training with the expert mode user program: Select the "Direction Change Detection Application" in expert mode and change the "Threshold comparison" parameter to 5.0. Upload it to SensorTile.box. In the mobile phone path:STMicroelectronics/logs...; lvqy ST MEMS Sensor Creative Design Competition

Transforming real-time Linux projects: How to use raw-os with linux to build real-time linux has been considered for 2 years. Several solutions have been considered, but none of them are universal. During this period, a feasible solution i...; jorya_txj Embedded System

Embedded system meaning and application: Abstract: This paper questions the currently popular definition of embedded systems in China , arguing that embedded systems are not "dedicated computer systems" and that embedded systems are not just...; sairvee Embedded System

【Perf-V Review】+ Design of simple functional programs (1): [i=s]This post was last edited by jinglixixi on 2021-3-24 09:30[/i]For beginners, the initial starting point is to start with building a development environment and testing routines, but if you really...; jinglixixi FPGA/CPLD

Detailed explanation of ZigBee networking principle: 1. Network OverviewBuilding a complete Zigbee mesh network includes two steps: network initialization and node joining the network. Node joining the network includes two steps: joining the network by ...; 灞波儿奔 RF/Wirelessly

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components