a
FEATURES
Gain of 20. Alterable from 1 to 160
Input CMR from Below Ground to 6 (V
S
– 1 V)
Output Span 20 mV to (V
S
– 0.2) V
1-, 2-, 3-Pole Low-Pass Filtering Available
Accurate Midscale Offset Capability
Differential Input Resistance 400 k
Drives 1 k Load to +4 V Using V
S
= +5 V
Supply Voltage: +3.0 V to +36 V
Transient Spike Protection and RFI Filters Included
Peak Input Voltage (40 ms): 60 V
Reversed Supply Protection: –34 V
Operating Temperature Range: –40 C to +125 C
APPLICATIONS
Current Sensing
Motor Control
Interface for Pressure Transducers, Position Indicators,
Strain Gages, and Other Low Level Signal Sources
Accelerometers
Single-Supply Sensor
Interface Amplifier
AD22057
FUNCTIONAL BLOCK DIAGRAM
+V
S
OFS
A1
A2
AD22057
IN+
A1
IN–
A2
OUT
GND
GENERAL DESCRIPTION
The AD22057 is a single-supply difference amplifier for ampli-
fying and low-pass filtering small differential voltages (typically
100 mV FS at a gain of 40) from sources having a large common-
mode voltage.
Supply voltages from +3.0 V to +36 V can be used. The input
common-mode range extends from below ground to +24 V using
a +5 V supply with excellent rejection of this common-mode
voltage. This is achieved by the use of a special resistive attenua-
tor at the input, laser trimmed to a very high differential balance.
Provisions are included for optional low-pass filtering and gain
adjustment. An accurate midscale offset feature allows bipolar
signals to be amplified.
+V
S
(CAR BATTERY)
SOLENOID
LOAD
+5V
ANALOG OUTPUT
4V PER AMP
100m
AD22057
200k
CMOS DRIVER
C
CORNER FREQUENCY
= 0.796Hz- F
CHASSIS
POWER
DARLINGTON
SINGLE-POLE LOW-PASS FILTERING, GAIN: 40
ANALOG GROUND
Figure 1. Typical Application Circuit for a Current Sensor Interface
REV. B
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otherwise under any patent or patent rights of Analog Devices.
AD22057–SPECIFICATIONS
(T = +25 C, V = +5 V, V
A
S
CM
= 0, R
L
= 10 k
unless otherwise noted)
Min
Typ
Max
+24
–1.0
80
80
180
280
9.7
+0.01
97
90
90
240
±
0.5
400
10.0
100
2.0
2.0
19.9
–62.5
–1
–12.5
0.49
2.5
7
5
20
20.0
0.03
0.50
3.0
11
30
0.2
0.2
20.1
+62.5
1
+12.5
0.51
25
27
Units
V
V
dB
dB
kΩ
%
kΩ
V/V
V
kΩ
V/V
V
Ω
V/V
ppm/°C
mV
µV/°C
V/V
kΩ
mA
mA
kHz
V/µs
µV/√Hz
Parameter
INPUTS (PINS 1 AND 8)
+CMR
CMR
CMRR
LF
CMRR
HF
R
INCM
R
MATCH
R
INDIFF
PREAMPLIFIER
G
CL
V
O
R
O
OUTPUT BUFFER
G
CL
V
O
R
O
OVERALL SYSTEM
G
V
OS
OFS
I
OSC
BW
–3 dB
SR
N
SD
PSR
Comments
Positive Common-Mode Range
Negative Common-Mode Range
Common-Mode Rejection Ratio
Common-Mode Rejection Ratio
Common-Mode Input Resistance
Matching of Resistances
Differential Input Resistance
Closed-Loop Gain
1
Output Voltage Range (Pin 3)
Output Resistance
2
Closed-Loop Gain
1
Output Voltage Range
3
Output Resistance (Pin 5)
Gain
1
Gain Drift
Input Offset Voltage
4
Offset Drift
Midscale Offset (Pin 7) Scaling
Input Resistance
Short-Circuit Output Current
–3 dB Bandwidth
Slew Rate
Noise Spectral Density
4
Power Supply Rejection
Input Offset Voltage
4
Gain
Operating Range
Quiescent Supply Range
5
Operating Temperature Range
8-Lead
SOIC (R-8)
Test Conditions
T
A
= T
MIN
to T
MAX
T
A
= T
MIN
to +85°C
f
≤
10 Hz
f = 1 kHz
Pin 1 or Pin 8 to Pin 2
Pin 1 to Pin 8
300
10.3
+4.8
103
2.06
+4.8
R
LOAD
≥
10 kΩ
V
O
≥
0.1 V dc
V
O
≥
0.1 V dc
T
A
= T
MIN
to T
MAX
T
A
= T
MIN
to T
MAX
Pin 7 to Pin 2
T
A
= T
MIN
to T
MAX
V
O
= +1 V dc
f = 100 Hz to 10 kHz
V
S
= 5 V, V
O
= 1 V to 4.2 V
V
S
= 24 V, V
O
= 1 V to 22 V
T
A
= T
MIN
to T
MAX
1.94
+0.02
V
OS
G
POWER SUPPLY
V
S
I
S
TEMPERATURE RANGE
T
OP
PACKAGE
20.0
0.05
T
A
= T
MIN
to T
MAX
T
A
= +25°C, V
S
= +5 V
3
5
200
36
500
µV/V
%/V
V
µA
°C
–40
+125
AD22057RZ
NOTES
1
Specified for default mode i.e., with no external components. The overall gain is trimmed to
±
0.5% while the individual gains of A1 and A2 may be subject to a
maximum
±
3% tolerance. Note that the actual gain in a particular application can be modified by the use of external resistor networks.
2
The actual output resistance of A1 is only a few ohms, but access to this output, via Pin 3, is always through a 100 k
Ω
resistor, which is trimmed to
±
3%.
3
For V
CM
≤
20 V. For V
CM
> 20 V, V
OL
1 mV/V
×
V
CM
.
4
Referred to the input (Pins 1 and 8).
5
With V
DM
= 0 V. Differential mode signals are referred to as V
DM
, while V
CM
refers to common-mode voltages.
Specifications subject to change without notice.
–2–
REV. B
AD22057
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Plastic SOIC Package
(R-8)
–IN
1
GND
2
8
+IN
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to +36 V
Peak Input Voltage (40 ms) . . . . . . . . . . . . . . . . . . . . . . +60 V
V
OFS
(Pin 7 to Pin 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20 V
Reversed Supply Voltage Protection . . . . . . . . . . . . . . . –34 V
Operating Temperature . . . . . . . . . . . . . . . . –40°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; the functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
7
OFFSET
TOP VIEW
A1
3
(Not to Scale)
6
+V
S
AD22057
A2
4
5
OUT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD22057 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PRODUCT DESCRIPTION
The AD22057 is a single-supply difference amplifier consisting
of a precision balanced attenuator, a very low drift preamplifier
and an output buffer amplifier (A1 and A2, respectively, in
Figure 2). It has been designed so that small differential sig-
nals (V
DM
in Figure 3) can be accurately amplified and filtered
in the presence of large common-mode voltages (V
CM
) without
the use of any other active components.
+V
S
OFS A1
A2
offset to an optional voltage of one half of that supplied to Pin 7;
in many cases this offset would be +V
S
/2 by tying Pin 7 to +V
S
(Pin 6), permitting the conditioning and processing of bipolar
signals (see Strain Gage Interface section).
The output buffer A2 has a gain of
×2,
setting the precalibrated,
overall gain of the AD22057, with no external components, to
×20.
(This gain is easily user-configurable—see Altering the
Gain section for details.)
The dynamic properties of the AD22057 are optimized for inter-
facing to transducers; in particular, current sensing shunt
resistors. Its rejection of large, high frequency, common-mode
signals makes it superior to that of many alternative approaches.
This is due to the very careful design of the input attenuator and
the close integration of this highly balanced, high impedance
system with the preamplifier.
APPLICATIONS
AD22057
IN+
A1
IN–
A2
OUT
GND
Figure 2. Simplified Schematic
The resistive attenuator network is situated at the input to the
AD22057 (Pins 1 and 8), allowing the common-mode voltage at
Pins 1 and 8 to be six times greater than that which can be toler-
ated by the actual input to A1. As a result, the input common-
mode range extends to 6× (V
S
– 1 V).
Two small filter capacitors (not shown in Figure 2) have been
included at the inputs of A1 to minimize the effects of any spuri-
ous RF signals present in the signal.
Internal feedback around A1 sets the closed-loop gain of the
preamplifier to
×10
from the input pins; the output of A1 is
connected to Pin 3 via a 100 kΩ resistor, which is trimmed to
±
3% (R12 in Figure 2) to facilitate the low-pass filtering of the
signal of interest (see Low-Pass Filtering section). The inclusion
of an additional resistive network allows the output of A1 to be
The AD22057 can be used wherever a high gain, single-supply
differencing amplifier is required, and where a finite input resis-
tance (240 kΩ to ground, 400 kΩ between differential inputs)
can be tolerated. In particular, the ability to handle a common-
mode input considerably larger than the supply voltage is fre-
quently of value.
Also, the output can run down to within 20 mV of ground,
provided it is not called on to sink any load current. Finally, the
output can be offset to half of a full-scale reference voltage (with
a tolerance of
±
2%) to allow a bipolar input signal.
ALTERING THE GAIN
The gain of the preamplifier, from the attenuator input (Pins 1
and 8) to its output at Pin 3, is
×10
and that of the output
buffer, from Pin 4 to Pin 5, is
×2,
thus making the overall de-
fault gain
×20.
The overall gain is accurately trimmed (to within
±
0.5%). In some cases, it may be desirable to provide for some
variation in the gain; for example, in absorbing the scaling error
of a transducer.
REV. B
–3–
AD22057
Figure 3 shows a general method for trimming the gain, either
upward or downward, by an amount dependent on the resistor,
R. The gain range, expressed as a percentage of the overall gain,
is given by (10 MΩ/R)%. Thus, the adjustment range would be
±
2% for R = 5 MΩ;
±
10% for R = 1 MΩ, etc.
ANALOG
OUTPUT
+IN
V
DM
OFS +V
S
OUT
AD22057
–IN GND A1
A2
R
GAIN ADJUST
20k MIN
ANALOG
COMMON
Increasing the Gain.
The gain can be raised by connecting a
resistor from the output of the buffer amplifier (Pin 5) to its
noninverting input (Pin 4) as shown in Figure 5. The gain is
now multiplied by the factor R/(R–100k); for example, it is
doubled for R = 200 kΩ. Overall gains of up to
×160
(R = 114 kΩ)
are readily achievable in this way. Note, however, that the accu-
racy of the gain becomes critically dependent on resistor value at
high gains. Also, the effective input offset voltage at Pins 1 and
8 (about six times the actual offset of A1) limits the part’s use in
very high gain, dc-coupled applications. The gain may be trimmed
by using a fixed and variable resistor in series (see, for example,
Figure 10).
ANALOG
OUTPUT
+IN OFS +V
S
OUT
V
DM
V
CM
(SEE TEXT)
V
DM
= DIFFERENTIAL VOLTAGE, V
CM
= COMMOM-MODE VOLTAGE
Figure 3. Altering Gain to Accommodate Transducer
Scaling Error
AD22057
–IN GND A1
A2
POINT X
(SEE TEXT)
20R
GAIN = –––––––––
R – 100k
R
GAIN
R = 100k –––––––––
GAIN – 20
ANALOG
COMMON
In addition to the method above, another method may be used
to vary the gain. Many applications will call for a gain higher
than
×20,
and some require a lower gain. Both of these situa-
tions are readily accommodated by the addition of one external
resistor, plus an optional potentiometer if gain adjustment is
required (for example, to absorb a calibration error in a trans-
ducer).
Decreasing the Gain.
See Figure 4. Since the output of the
preamplifier has an output resistance of 100 kΩ, an external
resistor connected from Pin 4 to ground will precisely lower the
gain by a factor R/(100k+R). When configuring the AD22057
for any gain, the maximum input and the power supply being
used should be considered, since either the preamplifier or the
output buffer will reach its full-scale output (approximately
V
S
– 0.2 V) with large differential input voltages. The input of
the AD22057 is limited to no greater than (V – 0.2)/10, for
overall gains less than 10, since the preamplifier, with its fixed
gain of
×10,
reaches its full scale output before the output
buffer. For V
S
= 5 V this is 0.48 V. For gains greater than 10,
however, the swing at the buffer output reaches its full-scale first
and limits the AD22057 input to (V
S
– 0.2)/G, where G is the
overall gain. Increasing the power supply voltage increases the
allowable maximum input. For V
S
= 5 V and a nominal gain of
20, the maximum input is 240 mV.
The overall bandwidth is unaffected by changes in gain using
this method, although there may be a small offset voltage due to
the imbalance in source resistances at the input to A2. In many
cases this can be ignored but, if desired, can be nulled by insert-
ing a resistor in series with Pin 4 (at “Point X” in Figure 4) of
value 100 kΩ minus the parallel sum of R and 100 kΩ. For
example, with R = 100 kΩ (giving a total gain of
×10),
the op-
tional offset nulling resistor is 50 kΩ.
ANALOG
OUTPUT
+IN
V
DM
OFS +V
S
OUT
V
CM
Figure 5. Achieving Gains Greater Than
×
20
Once again, a small offset voltage will arise from an imbalance
in source resistances and the finite bias currents inherently
present at the input of A2. In most applications this additional
offset error (about 130
µV
at
×40)
will be comparable with the
specified offset range and will therefore introduce negligible
skew. It may, however, be essentially eliminated by the addition
of a resistor in series with the parallel sum of R and 100 kΩ
(i.e., at “Point X” in Figure 5) so the total series resistance is
maintained at 100 kΩ. For example, at a gain of
×30,
when
R = 300 kΩ and the parallel sum of R and 100 kΩ is 75 kΩ, the
padding resistor should be 25 kΩ. A 50 kΩ pot would provide
an offset range of about
±
2.25 mV referred to the output, or
±
75
µV
referred to the attenuator input. A specific example is
shown in Figure 12.
LOW-PASS FILTERING
In many transducer applications it is necessary to filter the sig-
nal to remove spurious high frequency components, including
noise, or to extract the mean value of a fluctuating signal with a
peak-to-average ratio (PAR) greater than unity. For example, a
full wave rectified sinusoid has a PAR of 1.57, a raised cosine
has a PAR of 2 and a half wave sinusoid has a PAR of 3.14.
Signals having large spikes may have PARs of 10 or more.
When implementing a filter, the PAR should be considered so
the output of the AD22057 preamplifier (A1) does not clip
before A2 does, since this nonlinearity would be averaged and
appear as an error at the output. To avoid this error both ampli-
fiers should be made to clip at the same time. This condition is
achieved when the PAR is no greater than the gain of the second
amplifier (2 for the default configuration). For example, if a
PAR of 5 is expected, the gain of A2 should be increased to 5.
Low-pass filters can be implemented in several ways using the
features provided by the AD22057. In the simplest case, a
single-pole filter (20 dB/decade) is formed when the output of
A1 is connected to the input of A2 via the internal 100 kΩ resis-
tor by strapping Pins 3 and 4, and a capacitor added from this
node to ground, as shown in Figure 6. The dc gain remains
×20,
and the gain trim shown in Figure 3 may still be used. If a resis-
tor is added across the capacitor to lower the gain, the corner
–4–
REV. B
AD22057
–IN GND A1
A2
20R
GAIN = –––––––––
R + 100k
GAIN
R = 100k –––––––––
20 – GAIN
V
CM
R
POINT X
(SEE TEXT)
ANALOG
COMMON
Figure 4. Achieving Gains Less Than
×
20
AD22057
frequency will increase; it should be calculated using the parallel
sum of the resistor and 100 kΩ.
ANALOG
OUTPUT
1
100k
+IN OFS +V
S
OUT
V
DM
CORNER FREQUENCY =
THAT IS, 1.59Hz- F
AD22057
–IN GND A1
A2
2 C
A three-pole filter (with roll-off 60 dB/decade) can be formed by
adding a passive RC network at the output forming a real pole.
A three-pole filter with a corner frequency f
3
has the same
attenuation a one-pole filter of corner f
1
has at a frequency
√f
33
/f
1
, where the attenuation is 30 Log (f
3
/f
1
) (see the graph in
Figure 9). Using equal capacitor values, and a resistor of
160 kΩ, the corner-frequency calibration remains 1 Hz-µF.
FREQUENCY
ATTENUATION
(C IS IN FARADS)
V
CM
C
ANALOG
COMMON
–20dB/DECADE
–60dB/DECADE
Figure 6. Connections for Single-Pole, Low-Pass Filter
If the gain is raised using a resistor, as shown in Figure 5, the
corner frequency is lowered by the same factor as the gain is
raised. Thus, using a resistor of 200 kΩ (for which the gain
would be doubled) the corner frequency is now 0.796 Hz-µF,
(0.039
µF
for a 20 Hz corner).
ANALOG
OUTPUT
+IN OFS +V
S
OUT
V
DM
30LOG (f
3
/f
1
)
A 1-POLE FILTER, CORNER f
1
,
AND A 3-POLE FILTER, CORNER f
3
,
HAVE THE SAME ATTENUATION,
–30LOG (f
3
/f
1
), AT FREQUENCY (f
33
/f
1)
f
1
f
3
(f
33
/f
1
)
AD22057
–IN GND A1
A2
255k
C
CORNER
FREQUENCY = 1Hz- F
Figure 9. Comparative Responses of One- and Three-Pole
Low-Pass Filters
CURRENT SENSOR INTERFACE
V
CM
C
ANALOG
COMMON
A typical automotive application making use of the large
common-mode range is shown in Figure 10.
+V
S
(BATTERY)
SOLENOID
LOAD
FLYBACK
DIODE
+IN OFS +V
S
OUT
100m
191k
5% SENSOR
CALIBRATION
20k
CORNER FREQUENCY
= 0.796Hz- F
(0.22 F FOR f = 3.6Hz)
ANALOG COMMON
+5V
Figure 7. Connections for Conveniently Scaled, Two-Pole,
Low-Pass Filter
A two-pole filter (with a roll-off of 40 dB/decade) can be imple-
mented using the connections shown in Figure 7. This is a
Sallen & Key form based on a
×2
amplifier. It is useful to remem-
ber that a two-pole filter with a corner frequency f
2
and a
one-pole filter with a corner at f
1
have the same attenuation at
the frequency (f
22
/f
1
). The attenuation at that frequency is
40 Log(f
2
/f
1
). This is illustrated in Figure 8. Using the standard
resistor value shown, and equal capacitors (in Figure 7), the
corner frequency is conveniently scaled at 1 Hz-µF (0.05
µF
for
a 20 Hz corner). A maximally flat response occurs when the
resistor is lowered to 196 kΩ and the scaling is then 1.145 Hz-
µF.
The output offset is raised by about 4 mV (equivalent to
200
µV
at the input pins).
FREQUENCY
ATTENUATION
–40dB/DECADE
ANALOG OUTPUT
4V PER AMP
AD22057
–IN GND A1
A2
CMOS DRIVER
C
POWER
DARLINGTON
CHASSIS
Figure 10. Current Sensor Interface. Gain Is
×
40, Single-
Pole Low-Pass Filtering
–20dB/DECADE
40LOG (f
2
/f
1
)
A 1-POLE FILTER, CORNER f
1
,
AND A 2-POLE FILTER, CORNER f
2
,
HAVE THE SAME ATTENUATION,
–40LOG (f
2
/f
1
), AT FREQUENCY f
22
/f
1
The current in a load, here shown as a solenoid, is controlled by
a power transistor that is either cut off or saturated by a pulse at
its base; the duty-cycle of the pulse determines the average
current. This current is sensed in a small resistor. The aver-
age differential voltage across this resistor is typically 100 mV,
although its peak value will be higher by an amount that
depends on the inductance of the load and the control fre-
quency. The common-mode voltage, on the other hand, extends
from roughly 1 V above ground, when the transistor is satu-
rated, to about 1.5 V above the battery voltage, when the tran-
sistor is cut off and the diode conducts.
If the maximum battery voltage spikes up to +20 V, the common-
mode voltage at the input can be as high as 21.5 V. This can be
measured using even a +5 V supply for the AD22057.
f
1
f
2
(f
22
/f
1
)
Figure 8. Comparative Responses of One- and Two-Pole
Low-Pass Filters
REV. B
–5–
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