CMOSLDM-100T datasheet, PDF - EEWORLD Datasheet

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CMOSLDM-100T: DescriptionActive Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.150 INCH HEIGHT, DIP-14/8; Categorylogic logic; File Size1MB，2 Pages; ManufacturerEngineered Components Co.

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CMOSLDM-100T Overview

Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.150 INCH HEIGHT, DIP-14/8

CMOSLDM-100T Parametric

Parameter Name	Attribute value
Parts packaging code	DIP
package instruction	DIP, DIP14,.3
Contacts	14
Reach Compliance Code	unknown
Other features	TAP TO TAP DELAY TOL.[NS] VARIES; BURNED-IN TO LEVEL B OF MIL-STD-883; MAX RISE TIME CAPTURED
series	CMOS/TTL
JESD-30 code	R-XDIP-P8
length	20.32 mm
Logic integrated circuit type	ACTIVE DELAY LINE
Number of functions	1
Number of taps/steps	5
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	TRUE
Package body material	UNSPECIFIED
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
programmable delay line	NO
Prop。Delay @ Nom-Sup	100 ns
Certification status	Not Qualified
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	DUAL
Total delay nominal (td)	100 ns
width	7.62 mm
Base Number Matches	1

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CMOSLDM-100T Related Products

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Description	Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.150 INCH HEIGHT, DIP-14/8	Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.150 INCH HEIGHT, DIP-14/8	Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.150 INCH HEIGHT, DIP-14/8	Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.150 INCH HEIGHT, DIP-14/8	Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.150 INCH HEIGHT, DIP-14/8	Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.150 INCH HEIGHT, DIP-14/8	Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.150 INCH HEIGHT, DIP-14/8	Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.150 INCH HEIGHT, DIP-14/8
Parts packaging code	DIP	DIP	DIP	DIP	DIP	DIP	DIP	DIP
package instruction	DIP, DIP14,.3	DIP, DIP14,.3	DIP, DIP14,.3	DIP, DIP14,.3	DIP, DIP14,.3	DIP, DIP14,.3	DIP, DIP14,.3	DIP, DIP14,.3
Contacts	14	14	14	14	14	14	14	14
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
Other features	TAP TO TAP DELAY TOL.[NS] VARIES; BURNED-IN TO LEVEL B OF MIL-STD-883; MAX RISE TIME CAPTURED	TAP TO TAP DELAY TOL.[NS] VARIES; BURNED-IN TO LEVEL B OF MIL-STD-883; MAX RISE TIME CAPTURED	INPUT TO 1ST TAP DELAY = 16NS; BURNED-IN TO LEVEL B OF MIL-STD-883; MAX RISE TIME CAPTURED	INPUT TO 1ST TAP DELAY = 15NS; BURNED-IN TO LEVEL B OF MIL-STD-883; MAX RISE TIME CAPTURED	INPUT TO 1ST TAP DELAY = 15NS; BURNED-IN TO LEVEL B OF MIL-STD-883; MAX RISE TIME CAPTURED	TAP TO TAP DELAY TOL.[NS] VARIES; BURNED-IN TO LEVEL B OF MIL-STD-883; MAX RISE TIME CAPTURED	TAP TO TAP DELAY TOL.[NS] VARIES; BURNED-IN TO LEVEL B OF MIL-STD-883; MAX RISE TIME CAPTURED	TAP TO TAP DELAY TOL.[NS] VARIES; BURNED-IN TO LEVEL B OF MIL-STD-883; MAX RISE TIME CAPTURED
series	CMOS/TTL	CMOS/TTL	CMOS/TTL	CMOS/TTL	CMOS/TTL	CMOS/TTL	CMOS/TTL	CMOS/TTL
JESD-30 code	R-XDIP-P8	R-XDIP-P8	R-XDIP-P8	R-XDIP-P8	R-XDIP-P8	R-XDIP-P8	R-XDIP-P8	R-XDIP-P8
length	20.32 mm	20.32 mm	20.32 mm	20.32 mm	20.32 mm	20.32 mm	20.32 mm	20.32 mm
Logic integrated circuit type	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE
Number of functions	1	1	1	1	1	1	1	1
Number of taps/steps	5	5	5	5	5	5	5	5
Number of terminals	8	8	8	8	8	8	8	8
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Output polarity	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIP	DIP	DIP	DIP	DIP	DIP	DIP	DIP
Encapsulate equivalent code	DIP14,.3	DIP14,.3	DIP14,.3	DIP14,.3	DIP14,.3	DIP14,.3	DIP14,.3	DIP14,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE
power supply	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
programmable delay line	NO	NO	NO	NO	NO	NO	NO	NO
Prop。Delay @ Nom-Sup	100 ns	125 ns	26 ns	51 ns	59 ns	80 ns	85 ns	90 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	NO	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Total delay nominal (td)	100 ns	125 ns	26 ns	51 ns	59 ns	80 ns	85 ns	90 ns
width	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm
Base Number Matches	1	1	1	1	1	-	-	-

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