Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical values measured at V
CC
= 1.8V and T
A
= +25°C. Specifications guaranteed over specified operating conditions.)
(See
Operating Conditions
table.)
PARAMETER
Supply Current
Input Swing (IN)
Measured differentially at data source before
encountering loss (Point A in Figure 1) (Note 1)
400
V
CC
-
(IN
MAX
/4)
15
85
450
42
30
50
14
40
0.10
0.15
0.15
0.20
0.75
50
200
(Note 1)
(Note 1)
6.25
6.4
1.0
2.5
55
0.15
0.20
UI
0.25
0.30
1.0
ps
RMS
kHz
ps
Gbps
Gbps
100
115
800
58
dB
ps
mV
P-P
CONDITIONS
MIN
TYP
35
MAX
55
1600
V
CC
-
(IN
MIN
/4)
UNITS
mA
mV
P-P
V
dB
Input Common-Mode Voltage Range (Note 1)
Input Return Loss
Differential Input Resistance
Output Swing
Output Resistance
Output Return Loss
Output Transition Time (t
r
, t
f
)
100MHz to 3.2GHz, power off
IN+ and IN-
Measured differentially at OUT+ and OUT- with 50
±1%
load at each side
OUT+ or OUT-
100MHz to 3.2GHz, IN+ = high
20% to 80% (Note 2)
2.5Gbps, 3.2Gbps, 5.0Gbps; 0in to 30in FR-4
400mV
P-P
IN 1600mV
P-P
Residual Deterministic Jitter
(Notes 1, 3, 4)
2.5Gbps, 3.2Gbps; 40in FR-4
400mV
P-P
IN 1600mV
P-P
6.25Gbps; 0in to 30in FR-4
600mV
P-P
IN 1600mV
P-P
6.25Gbps; 0in to 30in FR-4
IN = 400mV
P-P
Output Random Jitter
Low-Frequency Cutoff Frequency
Latency
Maximum Bit Rate
Minimum Bit Rate
(Notes 1, 2)
Note 1:
Guaranteed by design and characterization.
Note 2:
Using input pattern 0000011111 at 6.25Gbps.
Note 3:
Difference in deterministic jitter between data source and equalizer output, evaluated at 2.5Gbps, 3.2Gbps, 5Gbps, and
6.25Gbps. Pattern used: PRBS (2
7
), ninety-six 0s, 1, 0, 1, 0, PRBS (2
7
), ninety-six 1s, 0, 1, 0, 1.
Note 4:
Signal is applied differentially at input to a 6-mil wide, loosely coupled stripline. Deterministic jitter at the output of the
transmission line is from media-induced loss, not from clock source modulation (see Figure 1).
All Digital Transistors High Gain Operational Amplifier Using Positive Feedback Technique Mezyad M. Amourah and Randall L. Geiger Dept. of Electrical and Computer Engineering Iowa State University, Am...
I use GPRS MODEM to connect to PC through serial port, and want to send the following data to mobile phone through MMS. 0.000 -0.145 -0.065 0.003 -0.145 -0.065 0.006 -0.145 -0.065 0.008 -0.145 -0.065 ...
1. Cooperate with others. Take our hardware engineers as an example. When testing, software cooperation is generally required. A task that is extremely complex for hardware may be just a few lines of ...
I recently used DSP2808 to make a 3.2 TFT LCD. The GPIO output is correct, but the TFT has no display. Please help~~This TFT works normally on ARM~
Is there any professional who can help?...