FUJITSU MICROELECTRONICS
DATA SHEET
DS05-13107-4E
Memory FRAM
CMOS
2 M Bit (256 K
×
8)
MB85R2001
■
DESCRIPTIONS
The MB85R2001 is an FRAM (Ferroelectric Random Access Memory) chip consisting of 262,144 words
×
8 bits
of non-volatile memory cells created using ferroelectric process and silicon gate CMOS process technologies.
The MB85R2001 is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85R2001 can be used for 10
10
read/write operations, which is a significant
improvement over the number of read and write operations supported by Flash memory and E
2
PROM.
The MB85R2001 uses a pseudo-SRAM interface that is compatible with conventional asynchronous SRAM.
■
FEATURES
•
•
•
•
•
•
Bit configuration
Read/write endurance
Operating power supply voltage
Operating temperature range
Data retention
Package
: 262,144 words
×
8 bits
: 10
10
times/bit
: 3.0 V to 3.6 V
:
−
40 °C to
+
85 °C
: 10 years (
+
55
°C)
: 48-pin plastic TSOP (1)
Copyright©2007-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.8
MB85R2001
■
PIN ASSIGNMENTS
(
TOP VIEW
)
A11
A9
NC
A8
A13
WE
CE2
A15
NC
V
CC
NC
NC
GND
NC
NC
V
CC
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OE
NC
GND
A10
CE1
NC
I/O8
I/O7
I/O6
I/O5
I/O4
V
CC
NC
I/O3
I/O2
I/O1
NC
NC
NC
A0
A1
GND
A2
A3
(FPT-48P-M25)
■
PIN DESCRIPTIONS
Pin name
A0 to A17
I/O1 to I/O8
CE1
CE2
WE
OE
V
CC
GND
NC
Address Input
Data Input/Output
Chip Enable 1 Input
Chip Enable 2 Input
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
Function
2
DS05-13107-4E
MB85R2001
■
BLOCK DIAGRAM
A0
·
·
·
Address Latch.
Row Dec.
Ferro Capacitor Cell
to
A17
Column Dec.
intCE2
S/A
CE2
intCEB
WE
OE
intCEB
CE1
·
·
I/O8
to
I/O1
intCE2
intOE
intWE
intCE2
I/O1 to I/O8
DS05-13107-4E
3
MB85R2001
■
FUNCTION TRUTH TABLE
Operation Mode
Standby Pre-charge
CE1
H
X
X
Read
Read
(Pseudo-SRAM, OE control*
1
)
Write
L
Write
(Pseudo-SRAM, WE control*
2
)
L
H
H
L
L
H
H
CE2
X
L
X
H
WE
X
X
H
H
H
L
H
Din
OE
X
X
H
L
Dout
Operation
(I
CC
)
High-Z
Standby
(I
SB
)
I/O1 to I/O8
Supply Current
L = V
IL
, H = V
IH
, X can be either V
IL
or V
IH
, High-Z = High Impedance
: Latch address and latch data at falling edge,
: Latch address and latch data at rising edge
*1 : OE control of the Pseudo-SRAM means the valid address at the falling edge of OE to read.
*2 : WE control of the Pseudo-SRAM means the valid address and data at the falling edge of WE to write.
4
DS05-13107-4E
MB85R2001
■
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage*
Input Voltage*
Output Voltage*
Ambient Operating Temperature
Storage Temperature
* : All voltages are referenced to GND
=
0 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Symbol
V
CC
V
IN
V
OUT
T
A
Tstg
Rating
Min
−0.5
−0.5
−0.5
−40
−40
Max
+4.0
V
CC
+
0.5
V
CC
+
0.5
+85
+125
Unit
V
V
V
°C
°C
■
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage*
Input Voltage (high)*
Input Voltage (low)*
Operating Temperature
Symbol
V
CC
V
IH
V
IL
T
A
Value
Min
3.0
V
CC
x 0.8
−0.5
−40
Typ
3.3
⎯
⎯
⎯
Max
3.6
V
CC
+
0.5
+0.8
+85
Unit
V
V
V
°C
* : All voltages are referenced to GND
=
0 V.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
WARNING:
DS05-13107-4E
5
京公网安备 11010802033920号
EEWORLD
