DM9102A
Single Chip Fast Ethernet NIC controller
General Description
The DM9102A is a fully integrated and cost-effective single
chip Fast Ethernet NIC controller. It is designed with the low
power and high performance process. It is a 3.3V device
with 5V tolerance then it supports 3.3V and 5V signaling.
The DM9102A provides direct interface to the PCI or the
CardBus. It supports bus master capability and fully
complies with PCI 2.2. In media side, The DM9102A
interfaces to the UTP3,4,5 in 10Base-T and UTP5 in
100Base-TX. It is fully compliance with the IEEE 802.3u
Spec. Its auto-negotiation function will automatically
configure the DM9102A to take the maximum advantage of
its abilities. The DM9102A is also support IEEE 802.3x full-
duplex flow control.
The DM9102A supports two types of power-management
mechanisms. The main mechanism is based upon the
OnNow architecture, which is required for PC99. The
alternative mechanism is based upon the remote Wake-On-
LAN mechanism.
Block Diagram
EEPROM
Interface
Boot ROM /
MII Interface
DMA
PHYceiver
MAC
Scrambler
4B/5B
Encoding
TX+/-
NRZI to MLT3
NRZ to NRZI
Parallel to
Serial
TX
Machine
MII
TX
FIFO
PCI
Interface
RX+/-
AEQ
MLT3 to NRZI
NRZI to NRZ
Parallel to
Serial
De-
Scrambler
4B/5B
Decoding
RX
Machine
RX
FIFO
LED Driver
Autonegotiation
MII Management Control
& MII Register
Power
Management
Block
PME#
WOL
Final
Version: DM9102A-DS-F03
August 28, 2000
1
DM9102A
Single Chip Fast Ethernet NIC controller
Table of Contents
General Description ............................................................. 1
Block Diagram...................................................................... 1
Features ............................................................................... 4
Pin Configuration: DM9102A 128pin QFP.......................... 5
Pin Configuration: DM9102A 128pin TQFP ....................... 6
Pin Description ..................................................................... 7
- PCI Bus and CardBus Interface Signals......................... 7
- Boot ROM and EEPROM Interface ................................ 8
Multiplex Mode ................................................................ 8
Direct Mode.................................................................... 10
- LED Pins......................................................................... 11
- Network Interface ........................................................... 12
- Miscellaneous Pins......................................................... 12
- Power Pins ..................................................................... 13
- Note: LED Mode ............................................................ 13
7. Network Operation Register (CR6)............................... 30
8. Interrupt Mask Register (CR7)...................................... 32
9. Statistical Counter Register (CR8)................................ 33
10. PROM & Management Access Register (CR9) ........ 34
11. Programming ROM Address Register (CR10) .......... 35
12. General Purpose Timer Register (CR11)................... 35
13. PHY Status Register (CR12) ...................................... 35
14. Sample Frame Access Register (CR13).................... 36
15. Sample Frame Data Register (CR14) ........................ 36
16. Watching & Jabber Timer Register (CR15)................ 36
✧
CardBus Status Changed Register .............................. 39
1. Function Event Register: (offset 80h)............................ 39
2. Function Event Mask Register: (offset 84h).................. 39
3. Function Present State Register: (offset 88h)............... 39
4. Function Force Event Register: (offset 8Ch) ................ 40
✧
PHY Management Register Set ................................... 41
Key To Default ................................................................... 41
Basic Mode Control Register (BMCR)
- Register 0......................................................................... 42
Basic Mode Status Register (BMSR)
- Register 1......................................................................... 43
PHY ID Identifier Register #1 (PHYIDR1)
- Register 2......................................................................... 44
PHY ID Identifier Register #2 (PHYIDR2)
- Register 3......................................................................... 44
Auto-negotiation Advertisement Register (ANAR)
- Register 4......................................................................... 44
Auto-negotiation Link Partner Ability Register (ANLPAR) -
Register 5........................................................................... 45
Auto-negotiation Expansion Register (ANER)
- Register 6......................................................................... 46
DAVICOM Specified Configuration Register (DSCR)
- Register 10....................................................................... 46
DAVICOM Specified Configuration and Status Register
(DSCSR) - Register 11...................................................... 47
10Base-T Configuration/Status (10BTSCRCSR)
- Register 12....................................................................... 48
Functional Description ....................................................... 49
✧
System Buffer Management ......................................... 49
1. Overview........................................................................ 49
2. Data Structure and Descriptor List ................................ 49
3. Buffer Management: Chain Structure Method.............. 49
5. Descriptor List: Buffer Descriptor Format...................... 49
(a). Receive Descriptor Format......................................... 49
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August 28, 2000
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Register Definition.............................................................. 14
✧
PCI Configuration Registers.......................................... 14
Key to Default..................................................................... 14
Identification ID............................................................... 15
Command & Status........................................................ 15
Revision ID ..................................................................... 17
Miscellaneous Function ................................................. 18
I/O Base Address........................................................... 18
Memory Mapped Base Address.................................... 19
Subsystem Identification ................................................ 19
CardBus CIS Pointer...................................................... 20
Expansion ROM Base Address..................................... 21
Capabilities Pointer......................................................... 21
Interrupt & Latency Configuration .................................. 22
Device Specific Configuration Register......................... 22
Power Management Register........................................ 23
Power Management Control/Status .............................. 24
✧
Control and Status Register (CR).................................. 25
Key to Default..................................................................... 25
1. System Control Register (CR0)..................................... 26
2. Transmit Descriptor Poll Demand (CR1)...................... 27
3. Receive Descriptor Poll Demand (CR2) ....................... 27
4. Receive Descriptor Base Address (CR3) ..................... 27
5. Transmit Descriptor Base Address (CR4) .................... 28
6. Network Status Report Register (CR5)......................... 28
DM9102A
Single Chip Fast Ethernet NIC controller
6. Example of DM9102A SROM Format.......................... 63
(b). Transmit Descriptor Format......................................... 51
✧
Initialization Procedure................................................... 54
Data Buffer Processing Algorithm ..................................... 54
1. Receive Data Buffer Processing ................................... 54
2. Transmit Data Buffer Processing .................................. 55
✧
Network Function........................................................... 56
1. Overview......................................................................... 56
2. Receive Process and State Machine............................ 56
a. Reception Initiation ....................................................... 56
b. Address Recognition.................................................... 56
c. Frame Decapsulation................................................... 56
3. Transmit Process and State Machine........................... 56
a. Transmit Initiation.......................................................... 56
b. Frame Encapsulation................................................... 56
c. Collision......................................................................... 56
4. Physical Layer Overview ............................................... 56
✧
Serial Management Interface ........................................ 57
Package Information (128 pin, QFP) ................................ 75
✧
Power Management ...................................................... 58
1. Overview......................................................................... 58
2. PCI Function Power Management Status .................... 58
3. The Power Management Operation ............................. 58
a. Detect Network Link State Change ............................. 58
b. Active Magic Packet Function...................................... 58
c. Active the Sample Frame Function ............................. 58
✧
Sample Frame Programming Guide............................. 60
Products............................................................................. 77
Serial ROM Overview........................................................ 61
1. Subsystem ID Block....................................................... 61
2. SROM Version............................................................... 62
3. Controller Count ............................................................. 62
4. Controller_X Information................................................ 62
5. Controller Information Body Pointed By Controller_X Info
Block Offset Item in Controller Information Header....... 62
Contact Windows............................................................... 77
Warning.............................................................................. 77
Package Information (128 pin, TQFP).............................. 76
Ordering Information.......................................................... 77
Disclaimer .......................................................................... 77
Company Overview........................................................... 77
External MII/SRL Interface ................................................ 66
The Sharing Pin Table....................................................... 66
Absolute Maximum Ratings .............................................. 68
Operating Conditions......................................................... 68
DC Electrical Characteristics ............................................. 69
AC Electrical Characteristics & Timing Waveforms.......... 70
PCI Clock Spec. Timing................................................. 70
Other PCI Signals Timing Diagram............................... 70
Multiplex Mode Boot ROM Timing................................ 71
Direct Mode Boot ROM Timing..................................... 72
EEPROM Timing........................................................... 72
TP Interface.................................................................... 73
Oscillator/Crystal Timing................................................ 73
Auto-negotiation and Fast Link Pulse Timing Parameters
........................................................................................ 73
Final
Version: DM9102A-DS-F03
August 28, 2000
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DM9102A
Single Chip Fast Ethernet NIC controller
Features
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Integrated Fast Ethernet MAC, Physical Layer and
transceiver in one chip.
128pin QFP/128pin TQFP with CMOS process.
+3.3V Power supply with +5V tolerant I/O.
Supports PCI and CardBus interfaces.
Comply with PCI specification 2.2.
PCI clock up to 40MHz.
PCI bus master architecture.
PCI bus burst mode data transfer.
Two large independent FIFO; receive FIFO & transmit
FIFO.
Up to 256K bytes Boot EPROM or Flash interface.
EEPROM 93C46 interface supports node ID accesses
configuration information and user define message.
Node address auto-load and reload.
Comply with IEEE 802.3u 100Base-TX and 802.3
10Base-T.
Comply with IEEE 802.3u auto-negotiation protocol for
automatic link type selection.
Full Duplex/Half Duplex capability.
Support IEEE 802.3x Full Duplex Flow Control
VLAN support.
Comply with ACPI and PCI Bus Power Management.
Supports the MII (Media Independent Interface).
Supports Wake-On-LAN function and remote wake-up
(Magic packet, Link Change and Microsoft
®
wake-up
frame).
Supports 4 Wake-On-LAN (WOL) signals (active high
pulse, active low pulse, active high , active low ).
High performance 100Mbps clock generator and data
recovery circuit.
Digital clock recovery circuit using advanced digital
algorithm to reduce jitter.
Adaptive equalization circuit and Baseline wandering
restoration circuit for 100Mbps receiver.
Provides Loopback mode for easy system diagnostics.
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Final
Version: DM9102A-DS-F03
August 28, 2000
Final
TXO-
AVDD
AVDD
AVDD
AVDD
PCICLK
AGND
AGND
PME#
DVDD
REQ#
RST#
ISOLATE#
AD28
DGND
GNT#
AD25
AD26
AD27
AD29
AD31
AD30
RXI+
RXI-
TXO+
INT#
128
126
127
124
123
115
112
109
125
122
121
118
117
116
114
113
111
110
108
107
106
105
119
120
104
103
AD24
CBE3#
BGRESG
SUBGND
DGND
X1/OSC
X2
DVDD
WOL/CSTSCHG
NC
NC
NC
NC
SPEED10#
SPEED100#
FDX#
LINK&ACT#
DGND
NC
NC
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
39
40
41
42
44
43
45
46
48
47
49
51
54
53
55
56
57
60
59
61
63
64
50
52
58
62
NC
DVDD
SELROM
EECS
EECK
EEDO
EEDI
DGND
TEST1
BPA1/PCIMODE# (MA1/PCIMODE#)
BPA0/WMODE2
BPCS#
TEST2
DVDD
BPAD7/LEDMODE (MD7/LEDMODE)
BPAD6
BPAD5
BPAD4
BPAD3
(MD6)
(MD5)
(MD4)
(MD3)
(MA0/WMODE)
(ROMCS)
(MA6/SELROM)
(MA5)
(MA4/EECK)
(MA3/EEDO)
(MA2)
(MA9)
(MA8)
(MA7)
MA15
MA14
(MA13/SPEED10#)
(MA12 / SPEED100#)
(MA11/FDX#)
(MA10/LINK&ACT#)
MA17
MA16
WOL/CSTSCHG
IDSEL
DVDD
DVDD
5
6
97
96
95
94
93
92
91
90
89
88
87
86
85
84
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
98
AD23
AD22
DGND
DGND
AD21
AD20
DVDD
AD19
AD18
DGND
AD17
AD16
DVDD
DVDD
CBE2#
FRAME#
DGND
IRDY#
TRDY#
DVDD
DEVSEL#
STOP#
DGND
DGND
PERR#
SERR#
DVDD
PAR
CBE1#
DGND
CLOCKRUN#
DGND
AD15
3
4
100
99
1
2
BGRES
102
101
August 28, 2000
Version: DM9102A-DS-F03
Pin Configuration : 128 pin QFP
DM9102A
AD9
AD8
AD7
AD6
AD4
AD3
AD2
AD1
AD0
Single Chip Fast Ethernet NIC controller
DM9102A
AD13
AD14
AD12
DVDD
DVDD
AD5
DVDD
DVDD
DGND
AD10
AD11
DGND
CBE0#
DGND
BPAD1 (MD1)
BPAD2 (MD2)
BPAD0 (MD0/EEDI)
5
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