Application specific programmable EMI reduction using spread
spectrum for clocks
Programmable PLLs for system frequency margin tests
Meets critical timing requirements in complex system designs
Suitability for PC, consumer, portable, and networking
applications
Capable of zero parts per million (PPM) frequency synthesis
error
Uninterrupted system operation during clock frequency switch
Application compatibility in standard and low-power systems
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Functional Description
For a complete list of related documentation, click
here.
Block Diagram
XIN
/
EXCLKIN
XOU
T
OSC
MU
X
and
Control
Logic
FS1
PLL 2
(SS)
PLL 1
(SS)
Crossbar
Switch
Output
Dividers
and
Drive
Strength
Control
CLK1
(SS)
REFOUT
(No SS)
FS0
CLK2
(SS)
SSON
PD#/OE
Note
1. The devices mentioned in this datasheet are available as factory-programmable parts and not as field-programmable parts, since the associated programming software
is currently not available. Visit
www.cypress.com
to create a Technical Support case, so Cypress can provide a programming file (.jed file) that matches your
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