Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MCF54455
Rev. 3, 12/2008
MCF54455
MAPBGA–256
17mm x 17mm
TEPBGA–360
23mm x 23mm
MCF5445x ColdFire
®
Microprocessor Data Sheet
Features
• Version 4 ColdFire
®
Core with MMU and EMAC
• Up to 410 Dhrystone 2.1 MIPS @ 266 MHz
• 16-KBytes instruction cache and 16-KBytes data cache
• 32-KBytes internal SRAM
• Support for booting from SPI-compatible flash, EEPROM,
and FRAM devices
• Crossbar switch technology (XBS) for concurrent access to
peripherals or RAM from multiple bus masters
• 16-channel DMA controller
• 16-bit 133-MHz DDR/mobile-DDR/DDR2 controller
• USB 2.0 On-the-Go controller with ULPI support
• 32-bit PCI controller @ 66MHz
• ATA/ATAPI controller
• 2 10/100 Ethernet MACs
• Coprocessor for acceleration of the DES, 3DES, AES,
MD5, and SHA-1 algorithms
• Random number generator
• Synchronous serial interface (SSI)
• 4 periodic interrupt timers (PIT)
• 4 32-bit timers with DMA support
• DMA-supported serial peripheral interface (DSPI)
• 3 UARTs
• I
2
C bus interface
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1
2
3
MCF5445x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . .4
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .5
3.1 Analog Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.2 Oscillator Power Filtering . . . . . . . . . . . . . . . . . . . . . . . .6
3.3 Supply Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . .6
3.3.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . .7
3.3.2 Power-Down Sequence . . . . . . . . . . . . . . . . . . . .7
Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .7
4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4.2 Pinout—256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .15
4.3 Pinout—360 TEPBGA. . . . . . . . . . . . . . . . . . . . . . . . . .16
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .17
5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .18
5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .19
5.5 ClockTiming Specifications . . . . . . . . . . . . . . . . . . . . . .20
5.6 Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . .22
5.7 FlexBus Timing Specifications . . . . . . . . . . . . . . . . . . .23
5.8 SDRAM AC Timing Characteristics. . . . . . . . . . . . . . . .25
PCI Bus Timing Specifications . . . . . . . . . . . . . . . . . . 27
5.9.1 Overshoot and Undershoot . . . . . . . . . . . . . . . 28
5.10 ULPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . 29
5.11 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 30
5.12 I
2
C Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 32
5.13 Fast Ethernet Timing Specifications . . . . . . . . . . . . . . 33
5.13.1 Receive Signal Timing Specifications . . . . . . . 33
5.13.2 Transmit Signal Timing Specifications . . . . . . . 34
5.13.3 Asynchronous Input Signal Timing Specifications34
5.13.4 MII Serial Management Timing Specifications . 35
5.14 32-Bit Timer Module Timing Specifications . . . . . . . . . 35
5.15 ATA Interface Timing Specifications. . . . . . . . . . . . . . . 36
5.16 DSPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . 36
5.17 SBF Timing Specifications. . . . . . . . . . . . . . . . . . . . . . 38
5.18 General Purpose I/O Timing Specifications. . . . . . . . . 39
5.19 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 40
5.20 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 42
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.9
4
5
6
7
8
9
MCF5445x ColdFire
®
Microprocessor Data Sheet, Rev. 3
2
Freescale Semiconductor
MCF54455
JTAG
Version 4 ColdFire Core
16K
Instruction
Cache
16K
Data
Cache
EMAC
BDM
Oscillator
PLL
2 FECs
USB OTG
32K
SRAM
Hardware
Divide
CAU
MMU
eDMA
PCI
Serial Boot
Crossbar Switch (XBS)
Peripheral Bridge
ATA
DSPI
SSI
I
2
C
RNG
RTC
GPIO
SDRAM
Controller
FlexBus
EPORT
Watchdog
2 INTCs
4 PITs
3 UARTs
4 DMA
Timers
LEGEND
ATA
BDM
CAU
DSPI
eDMA
EMAC
EPORT
FEC
GPIO
I
2
C
–
Advanced Technology Attachment Controller
– Background debug module
– Cryptography acceleration unit
– DMA serial peripheral interface
– Enhanced direct memory access
– Enchance multiply-accumulate unit
– Edge port module
– Fast Ethernet Controller
– General Purpose Input/Output Module
– Inter-Intergrated Circuit
INTC
JTAG
MMU
PCI
PIT
PLL
RNG
RTC
SSI
USB OTG
–
Interrupt controller
– Joint Test Action Group interface
– Memory management unit
– Peripheral Component Interconnect
– Programmable interrupt timers
– Phase locked loop module
– Random Number Generator
– Real time clock
– Synchronous Serial Interface
– Universal Serial Bus On-the-Go controller
Figure 1. MCF54455 Block Diagram
MCF5445x ColdFire
®
Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
3
MCF5445x Family Comparison
1
MCF5445x Family Comparison
Table 1. MCF5445x Family Configurations
Module
MCF54450
•
MCF54451
•
MCF54452
•
MCF54453
•
MCF54454
•
MCF54455
•
The following table compares the various device derivatives available within the MCF5445x family.
ColdFire Version 4 Core with EMAC
(Enhanced Multiply-Accumulate Unit)
Core (System) Clock
Peripheral Bus Clock
(Core clock
÷
2)
External Bus Clock
(Core clock
÷
4)
Performance (Dhrystone/2.1 MIPS)
Independent Data/Instruction Cache
Static RAM (SRAM)
PCI Controller
Cryptography Acceleration Unit (CAU)
ATA Controller
DDR SDRAM Controller
FlexBus External Interface
USB 2.0 On-the-Go
UTMI+ Low Pin Interface (ULPI)
Synchronous Serial Interface (SSI)
Fast Ethernet Controller (FEC)
UARTs
I
2
C
DSPI
Real Time Clock
32-bit DMA Timers
Watchdog Timer (WDT)
Periodic Interrupt Timers (PIT)
Edge Port Module (EPORT)
Interrupt Controllers (INTC)
16-channel Direct Memory Access (DMA)
General Purpose I/O Module (GPIO)
JTAG — IEEE
®
1149.1 Test Access Port
Package
up to 240 MHz
up to 120 MHz
up to 60 MHz
up to 370
up to 266 MHz
up to 133 MHz
up to 66 MHz
up to 410
16 KBytes each
32 KBytes
•
—
—
•
•
•
•
•
1
3
•
•
•
4
•
4
•
2
•
•
•
•
•
—
•
•
•
•
•
1
3
•
•
•
4
•
4
•
2
•
•
•
•
—
—
•
•
•
•
•
2
3
•
•
•
4
•
4
•
2
•
•
•
•
•
—
•
•
•
•
•
2
3
•
•
•
4
•
4
•
2
•
•
•
•
—
•
•
•
•
•
•
2
3
•
•
•
4
•
4
•
2
•
•
•
•
•
•
•
•
•
•
•
2
3
•
•
•
4
•
4
•
2
•
•
•
256 MAPBGA
360 TEPBGA
MCF5445x ColdFire
®
Microprocessor Data Sheet, Rev. 3
4
Freescale Semiconductor
Ordering Information
2
Ordering Information
Table 2. Orderable Part Numbers
Freescale Part
Number
MCF54450VM180
MCF54450 Microprocessor
MCF54450VM240
256 MAPBGA
MCF54451CVM180
MCF54451 Microprocessor
MCF54451VM240
MCF54452CVR200
MCF54452 Microprocessor
MCF54452VR266
MCF54453CVR200
MCF54453 Microprocessor
MCF54453VR266
360 TEPBGA
MCF54454CVR200
MCF54454 Microprocessor
MCF54454VR266
MCF54455CVR200
MCF54455 Microprocessor
MCF54455VR266
266 MHz
266 MHz
200 MHz
200 MHz
266 MHz
266 MHz
200 MHz
240 MHz
200 MHz
180 MHz
240 MHz
Description
Package
Speed
180 MHz
Temperature
0
°
to +70
°
C
–40
°
to +85
°
C
0
°
to +70
°
C
–40
°
to +85
°
C
0
°
to +70
°
C
–40
°
to +85
°
C
0
°
to +70
°
C
–40
°
to +85
°
C
0
°
to +70
°
C
–40
°
to +85
°
C
0
°
to +70
°
C
3
3.1
Hardware Design Considerations
Analog Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for the analog V
DD
pins (VDD_A_PLL,
VDD_RTC). The filter shown in
Figure 2
should be connected between the board IV
DD
and the analog pins. The resistor and
capacitors should be placed as close to the dedicated analog V
DD
pin as possible. The 10-Ω resistor in the given filter is required.
Do not implement the filter circuit using only capacitors. The analog power pins draw very little current. Concerns regarding
voltage loss across the 10-ohm resistor are not valid.
10
Ω
Board IV
DD
10 µF
0.1 µF
Analog V
DD
Pin
GND
Figure 2. System Analog V
DD
Power Filter
MCF5445x ColdFire
®
Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
5
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