NAND08GW3B2DN1E datasheet, PDF

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NAND08GW3B2DN1E: Description512M X 8 FLASH 3V PROM, 25000 ns, PDSO48; Categorystorage; File Size2MB，69 Pages; ManufacturerNumonyx ( Micron ); Websitehttps://www.micron.com

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NAND08GW3B2DN1E Overview

512M X 8 FLASH 3V PROM, 25000 ns, PDSO48

NAND08GW3B2DN1E Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	48
Minimum operating temperature	-40 Cel
Maximum operating temperature	85 Cel
Rated supply voltage	3 V
Minimum supply/operating voltage	2.7 V
Maximum supply/operating voltage	3.6 V
Processing package description	12 X 20 MM, LEAD FREE, PLASTIC, TSOP-48
state	Transferred
ype	NAND TYPE
sub_category	Flash Memories
ccess_time_max	25000 ns
command_user_interface	YES
data_polling	NO
jesd_30_code	R-PDSO-G48
storage density	4.29E9 bit
Memory IC type	FLASH
memory width	8
umber_of_sectors_size	4K
Number of digits	5.37E8 words
Number of digits	512M
operating mode	ASYNCHRONOUS
organize	512MX8
Packaging Materials	PLASTIC/EPOXY
ckage_code	TSSOP
ckage_equivalence_code	TSSOP48,.8,20
packaging shape	RECTANGULAR
Package Size	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
ge_size__words_	2K
serial parallel	PARALLEL
wer_supplies__v_	3/3.3
gramming_voltage__v_	3
qualification_status	COMMERCIAL
eady_busy	YES
seated_height_max	1.2 mm
sector_size__words_	128K
standby_current_max	5.00E-5 Amp
Maximum supply voltage	0.0300 Amp
surface mount	YES
Craftsmanship	CMOS
Temperature level	INDUSTRIAL
terminal coating	NOT SPECIFIED
Terminal form	GULL WING
Terminal spacing	0.5000 mm
Terminal location	DUAL
ggle_bi	NO
length	18.4 mm
width	12 mm

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NAND04G-B2D, NAND08G-BxC

4 Gbit, 8 Gbit, 2112 byte/1056 word page

multiplane architecture, 1.8 V or 3 V, NAND Flash memories

Preliminary Data

Features

■

High density NAND Flash Memory

– Up to 8 Gbit memory array

– Cost-effective solution for mass storage

applications

NAND interface

– x8 or 16x bus width

– Multiplexed address/data

Supply voltage: 1.8 V or 3.0 V device

Page size

– x8 device: (2048 + 64 spare) bytes

– x16 device: (1024 + 32 spare) words

Block size

– x8 device: (128K + 4 K spare) bytes

– x16 device: (64K + 2 K spare) words

Multiplane architecture

– Array split into two independent planes

– Program/erase operations can be

performed on both planes at the same time

Page read/program

– Random access: 25 µs (max)

– Sequential access: 25 ns (min)

– Page program time: 200 µs (typ)

– Multiplane page program time (2 pages):

200 µs (typ)

Copy back program with automatic error

detection code (EDC)

Cache read mode

Fast block erase

– Block erase time: 1.5 ms (typ)

– Multiblock erase time (2 blocks):

1.5 ms (typ)

Status Register

Electronic signature

Chip Enable ‘don’t care’

Serial number option

NAND08G-BxC

TSOP48 12 x 20 mm (N)

LGA

■

LGA52 12 x 17 mm (ZL)

■

Data protection:

– Hardware program/erase disabled during

power transitions

– Non-volatile protection option

ONFI 1.0 compliant command set

Data integrity

– 100 000 program/erase cycles (with ECC

(error correction code))

– 10 years data retention

ECOPACK

packages

Device Summary

Part number

NAND04GR3B2D

■

Table 1.

Reference

■

NAND04G-B2D

NAND04GW3B2D

NAND04GR4B2D

(1)

NAND04GW4B2D

(1)

NAND08GR3B2C,

NAND08GW3B2C

NAND08GR4B2C

(1)

NAND08GW4B2C

(1)

NAND08GR3B4C

NAND08GW3B4C

■

1. x16 organization only available for MCP products.

December 2007

Rev 3

1/69

www.numonyx.com

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

Contents

NAND04G-B2D, NAND08G-BxC

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

3.10

3.11

Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Inputs/Outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1

4.2

4.3

4.4

4.5

4.6

Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1

Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1.1

6.1.2

Random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.2

Cache read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2/69

NAND04G-B2D, NAND08G-BxC

Contents

6.3

Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.3.1

6.3.2

Sequential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Random data input in page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.4

6.5

6.6

6.7

6.8

6.9

6.10

6.11

Multiplane page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Multiplane copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Multiplane block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Error detection code (EDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.11.1

6.11.2

6.11.3

6.11.4

6.11.5

Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

P/E/R Controller and cache ready/busy bit (SR6) . . . . . . . . . . . . . . . . . 34

P/E/R Controller bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SR4, SR3, SR2 and SR1 are reserved . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.12

6.13

6.14

6.15

6.16

Read status enhanced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Read EDC Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Read parameter page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Concurrent operations and extended read status . . . . . . . . . . . . . . . . 43

Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.1

9.2

9.3

9.4

9.5

Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

NAND Flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 48

3/69

NAND04G-B2D, NAND08G-BxC

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Device Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Address insertion (x8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Address insertion (x16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Address definition (x8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Address definition (x16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Copy back program addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Address definition for EDC units (x8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Address definition for EDC units (x16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

EDC Status Register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Electronic signature byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Electronic signature byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Electronic signature byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Parameter page data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Extended Read Status Register commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Block failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Program erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . . 48

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

DC characteristics (1.8 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

DC characteristics (3 V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

AC characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 65

LGA52 12 x 17 mm, 1 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 66

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5/69

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