NAND08GW3C2BZL1F datasheet, PDF

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NAND08GW3C2BZL1F: Description8 or 16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory; Categorystorage storage; File Size1MB，60 Pages; ManufacturerNumonyx ( Micron ); Websitehttps://www.micron.com; Environmental Compliance

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NAND08GW3C2BZL1F Overview

8 or 16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory

NAND08GW3C2BZL1F Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Numonyx ( Micron )
Parts packaging code	LGA
package instruction	VBGA, LGA52(UNSPEC)
Contacts	52
Reach Compliance Code	unknow
ECCN code	3A991.B.1.A
Maximum access time	25 ns
command user interface	YES
Data polling	NO
JESD-30 code	R-PBGA-B52
length	17 mm
memory density	8589934592 bi
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of departments/size	4K
Number of terminals	52
word count	1073741824 words
character code	1000000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1GX8
Package body material	PLASTIC/EPOXY
encapsulated code	VBGA
Encapsulate equivalent code	LGA52(UNSPEC)
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE
page size	2K words
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3/3.3 V
Programming voltage	3 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	0.65 mm
Department size	256K
Maximum standby current	0.00005 A
Maximum slew rate	0.03 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
switch bit	NO
type	MLC NAND TYPE
width	12 mm

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NAND08GW3C2B

NAND16GW3C4B

8 or 16 Gbit, 2112 byte page,

3 V supply, multilevel, multiplane, NAND Flash memory

Target Specification

Features

■

High density multilevel cell (MLC) Flash

memory

– Up to 16 Gbit memory array

– Up to 512 Mbit spare area

– Cost-effective solutions for mass storage

applications

NAND interface

– x8 bus width

– Multiplexed address/data

Supply voltage: V

= 2.7 to 3.6 V

Page size: (2048 + 64 spare) bytes

Block size: (256K + 8K spare) bytes

Multiplane architecture

– Array split into two independent planes

– Program/erase operations can be

performed on both planes at the same time

Memory cell array:

(2 K + 64 ) bytes x 128 pages x 4096 blocks

Page read/program

– Random access: 60 µs (max)

– Sequential access: 25 ns (min)

– Page program operation time: 800 µs (typ)

Multipage program time (2 pages): 800 µs (typ)

Copy-back program

– Fast page copy

Fast block erase

– Block erase time: 2.5 ms (typ)

Multiblock erase time (2 blocks): 2.5 ms (typ)

Status register

Electronic signature

■

TSOP48 12 x 20 mm (N)

■

LGA52 12 x 17 mm (N)

■

Serial number option

Chip enable ‘don’t care’

Data protection

– Hardware program/erase locked during

power transitions

Development tools

– Error correction code models

– Bad block management and wear leveling

algorithm

– HW simulation models

Data integrity

– 10,000 program/erase cycles (with ECC)

– 10 years data retention

ECOPACK

packages available

■

March 2008

Rev 2

1/60

www.numonyx.com

This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.

NAND08GW3C2B, NAND16GW3C4B

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1

Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

3.10

Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Chip Enable (E

, E

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Ready/Busy (RB

, RB

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1

4.2

4.3

4.4

4.5

4.6

Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1

6.2

6.3

6.4

Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2/60

NAND08GW3C2B, NAND16GW3C4B

6.5

6.6

6.7

6.8

6.9

6.10

6.11

6.12

6.13

Sequential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Copy-back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Multiplane copy-back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Multiplane page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Multiplane block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.13.1

6.13.2

6.13.3

Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

P/E/R controller bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.14

Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Concurrent operations and ERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.1

9.2

9.3

9.4

9.5

Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

NAND Flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.5.1

9.5.2

Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 41

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

12.1

Ready/Busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 54

Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3/60

NAND08GW3C2B, NAND16GW3C4B

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Address insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Address definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Paired page address information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Device identifier codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Electronic signature byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Electronic signature byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Electronic signature byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Extended Read Status Register commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Program and erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . 41

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

AC characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 56

LGA52 12 x 17 mm, 1 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 57

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5/60

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