NLU1G00
Single 2-Input NAND Gate
The NLU1G00 MiniGatet is an advanced high−speed CMOS
2−input NAND gate in ultra−small footprint.
The NLU1G00 input and output structures provide protection when
voltages up to 7.0 V are applied, regardless of the supply voltage.
Features
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MARKING
DIAGRAMS
Q
F
Q
UDFN6
1.2 x 1.0
CASE 517AA
UDFN6
1.0 x 1.0
CASE 517BX
1
IN B
1
6
V
CC
UDFN6
1.45 x 1.0
CASE 517AQ
1
IN A
2
5
NC
T
M
GND
3
4
OUT Y
= Device Marking
= Date Code
M
•
•
•
•
•
•
•
High Speed: t
PD
= 3.5 ns (Typ) @ V
CC
= 5.0 V
Low Power Dissipation: I
CC
= 1
mA
(Max) at T
A
= 25°C
Power Down Protection Provided on inputs
Balanced Propagation Delays
Overvoltage Tolerant (OVT) Input and Output Pins
Ultra−Small Packages
These are Pb−Free Devices
1
M
M
ORDERING INFORMATION
Figure 1. Pinout
(Top View)
IN A
IN B
&
See detailed ordering and shipping information on page 4 of
this data sheet.
OUT Y
Figure 2. Logic Symbol
PIN ASSIGNMENT
1
2
3
4
5
6
IN B
IN A
GND
OUT Y
NC
V
CC
FUNCTION TABLE
Input
A
L
L
H
H
B
L
H
L
H
Output
Y
H
H
H
L
©
Semiconductor Components Industries, LLC, 2016
June, 2016
−
Rev. 3
1
Publication Order Number:
NLU1G00/D
NLU1G00
MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
MSL
F
R
I
LATCHUP
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current Per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Moisture Sensitivity
Flammability Rating
Oxygen Index: 28 to 34
V
IN
< GND
V
OUT
< GND
Parameter
Value
−0.5
to +7.0
−0.5
to +7.0
−0.5
to +7.0
−20
±20
±12.5
±25
±25
−65
to +150
260
150
Level 1
UL 94 V−0 @ 0.125 in
±500
mA
Unit
V
V
V
mA
mA
mA
mA
mA
°C
°C
°C
Latchup Performance Above V
CC
and Below GND at 125°C (Note 2)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
2. Tested to EIA / JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
V
OUT
T
A
Dt/DV
Positive DC Supply Voltage
Digital Input Voltage
Output Voltage
Operating Free−Air Temperature
Input Transition Rise or Fall Rate
V
CC
= 3.3 V
±
0.3 V
V
CC
= 5.0 V
±
0.5 V
Parameter
Min
1.65
0
0
−55
0
0
Max
5.5
5.5
5.5
+125
100
20
Unit
V
V
V
°C
ns/V
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2
NLU1G00
DC ELECTRICAL CHARACTERISTICS
V
CC
(V)
1.65
2.3 to
5.5
V
IL
Low−Level
Input Voltage
1.65
2.3 to
5.5
V
OH
High−Level
Output Voltage
V
IN
= V
IH
or V
IL
I
OH
=
−50
mA
V
IN
= V
IH
or V
IL
I
OH
=
−4
mA
I
OH
=
−8
mA
V
OL
Low−Level
Output Voltage
V
IN
= V
IH
or V
IL
I
OL
= 50
mA
V
IN
= V
IH
or V
IL
I
OL
= 4 mA
I
OL
= 8 mA
I
IN
I
CC
Input Leakage
Current
Quiescent
Supply Current
0
v
V
IN
v
5.5 V
V
IN
= 5.5 V or
GND
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
0 to
5.5
5.5
1.9
2.9
4.4
2.58
3.94
0
0
0
0.1
0.1
0.1
0.36
0.36
±0.1
1.0
2.0
3.0
4.5
T
A
= 25
5C
Min
0.75 x
V
CC
0.70 x
V
CC
0.25 x
V
CC
0.30 x
V
CC
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
±1.0
10
Typ
Max
T
A
=
+855C
Min
0.75 x
V
CC
0.70 x
V
CC
0.25 x
V
CC
0.30 x
V
CC
1.9
2.9
4.4
2.34
3.66
0.1
0.1
0.1
0.52
0.52
±1.0
40
mA
mA
0.25 x
V
CC
0.30 x
V
CC
V
V
Max
T
A
=
−555C
to
+1255C
Min
Max
Unit
V
Symbol
V
IH
Parameter
Low−Level
Input Voltage
Conditions
V
V
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
= 3.0 nS)
V
CC
(V)
3.0 to
3.6
4.5 to
5.5
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
(Note 3)
5.0
Test
Condition
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
T
A
= 25
5C
Min
Typ
4.1
5.9
3.5
4.2
5.5
11
Max
8.8
12.3
5.9
7.9
10
T
A
=
+855C
Min
Max
10.5
14
7.0
9.0
10
T
A
=
−555C
to
+1255C
Min
Max
12.5
16.5
9.0
11
10
pF
pF
Unit
ns
Symbol
t
PLH
,
t
PHL
Parameter
Propagation Delay,
Input A or B to
Output Y
3. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the dynamic operating current consumption without
load. Average operating current can be obtained by the equation I
CC(OPR)
= C
PD
•
V
CC
•
f
in
+ I
CC
. C
PD
is used to determine the no−load
dynamic power consumption: P
D
= C
PD
•
V
CC2
•
f
in
+ I
CC
•
V
CC.
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3
NLU1G00
V
CC
INPUT
GND
t
PLH
Output Y
50% V
CC
t
PHL
V
OH
V
OL
*Includes all probe and jig capacitance.
A 1−MHz square input wave is recommended
for propagation delay tests.
C
L*
OUTPUT
Input A or B
50%
50% V
CC
Figure 3. Switching Waveforms
Figure 4. Test Circuit
ORDERING INFORMATION
Device
NLU1G00MUTCG
(In Development)
NLU1G00AMUTCG
NLU1G00CMUTCG
(In Development)
Package
UDFN6, 1.2 x 1.0, 0.4P
(Pb−Free)
UDFN6, 1.45 x 1.0, 0.5P
(Pb−Free)
UDFN6, 1.0 x 1.0, 0.35P
(Pb−Free)
Shipping
†
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
NLU1G00
PACKAGE DIMENSIONS
UDFN6, 1.2x1.0, 0.4P
CASE 517AA−01
ISSUE D
EDGE OF PACKAGE
D
A
B
L1
2X
0.10 C
2X
0.10 C
0.10 C
(A3)
A
A1
10X
0.08 C
SIDE VIEW
A1
5X
1
3
SEATING
PLANE
C
L
L2
6X
b
0.10 C A B
0.05 C
NOTE 3
6
4
e
BOTTOM VIEW
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5
ÉÉÉ
ÉÉÉ
ÉÉÉ
DETAIL B
Side View
(Optional)
0.40
PITCH
ÉÉ
ÉÉ
PIN ONE
REFERENCE
E
DETAIL A
Bottom View
(Optional)
EXPOSED Cu
MOLD CMPD
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND
0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
DIM
A
A1
A3
b
D
E
e
L
L1
L2
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.127 REF
0.15
0.25
1.20 BSC
1.00 BSC
0.40 BSC
0.30
0.40
0.00
0.15
0.40
0.50
TOP VIEW
A3
MOUNTING FOOTPRINT*
0.42
6X
0.22
6X
1.07
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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