MP7542
5 V CMOS
4-Bit Input, 12-Bit
Digital-to-Analog Converter
FEATURES
•
12-Bit DAC with a 4-Bit Parallel Address for 4 & 8-Bit
Microprocessor or Microcontroller Interface
•
Nonlinearity +1/2 LSB Tmin to Tmax
•
Latch-Up Free
•
Low Sensitivity to Output Amplifier V
OS
•
Low Output Capacitance
•
•
•
•
+5 V Supply Operation
Low Power Consumption: 40mW Max.
Low Cost
Serial Version: MP7543
GENERAL DESCRIPTION
The MP7542 is a precision, 12-bit CMOS 4-quadrant multi-
plying Digital-to-Analog Converter designed for direct interface
to 4 and 8-bit microprocessors.
The MP7542 consists of three 4-bit registers, a 12-bit DAC
register, address decoding logic, and a 12-bit CMOS multiplying
DAC. Data is loaded into the data registers in three 4-bit nibbles
and subsequently transferred to the 12-bit DAC register. All data
loading or data transfer operations are identical to the WRITE
cycle of a static RAM. A CLEAR input allows the 12-bit DAC reg-
ister to be reset to all zeros.
The MP7542 is manufactured using advanced thin-film on
monolithic double metal CMOS fabrication process. A unique
decoding technique is utilized yielding excellent accuracy and
stability.
The MP7542 reduces the additional linearity errors due to
output amplifier offset to only 330
µ
V per millivolt of offset versus
670
µ
V for the standard R-2R ladder CMOS DACs.
SIMPLIFIED BLOCK DIAGRAM
V
REF
R
FB
12-Bit Multiplying DAC
I
OUT1
I
OUT2
AGND
CLR
WR
CS
A0
A1
DB0 (LSB)
DB1
DB2
DB3 (MSB)
Address
Decode
Logic
H-Byte
Data
Register
M-Byte
Data
Register
L-Byte
Data
Register
12-Bit DAC Register
V
DD
DGND
Rev. 2.00
1
MP7542
ORDERING INFORMATION
Package
Type
Plastic Dip
Plastic Dip
SOIC
SOIC
Ceramic Dip
Ceramic Dip
Ceramic Dip
Ceramic Dip
Temperature
Range
–40 to +85
°
C
–40 to +85
°
C
–40 to +85
°
C
–40 to +85
°
C
–40 to +85
°
C
–40 to +85
°
C
–55 to +125
°
C
–55 to +125
°
C
Part No.
MP7542JN
MP7542KN
MP7542JS
MP7542KS
MP7542AD
MP7542BD
MP7542SD*
MP7542TD*
INL
(LSB)
+1
+1/2
+1
+1/2
+1
+1/2
+1
+1/2
DNL
(LSB)
+2
+1
+2
+1
+2
+1
+2
+1
Gain Error
(LSB)
+14.5
+14.5
+14.5
+14.5
+14.5
+14.5
+14.5
+14.5
*Contact factory for non-compliant military processing
PIN CONFIGURATIONS
See Packaging Section for Package Dimensions
I
OUT1
I
OUT2
AGND
DB3
DB2
DB1
DB0
CS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R
FB
V
REF
V
DD
CLR
DGND
A1
A0
WR
I
OUT1
I
OUT2
AGND
DB3
DB2
DB1
DB0
CS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R
FB
V
REF
V
DD
CLR
DGND
A1
A0
WR
16 Pin CDIP, PDIP (0.300”)
D16, N16
16 Pin SOIC (Jedec, 0.300”)
S16
PIN OUT DEFINITIONS
PIN NO.
1
2
3
4
5
6
7
NAME
I
OUT1
I
OUT2
AGND
DB3
DB2
DB1
DB0
DESCRIPTION
DAC current output. Normally
terminated at op amp.
DAC current output. Normally
terminated at ground.
Analog Ground
Data Input Bit 3 (MSB)
Data Input Bit 2
Data Input Bit 1
Data Input Bit 0 (LSB)
PIN NO.
8
9
10
11
12
13
14
15
16
NAME
CS
WR
A0
A1
DGND
CLR
V
DD
V
REF
R
FB
DESCRIPTION
Chip Select Input
Write Input
Address Bus Input
Address Bus Input
Digital Ground
Clear Input
+5 V Supply Input
Reference Input
DAC Feedback Resistor
Rev. 2.00
2
MP7542
ELECTRICAL CHARACTERISTICS
(V
DD
= + 5 V, V
REF
= +10 V unless otherwise noted)
25
°
C
Typ
Tmin to Tmax
Min
Max
Parameter
STATIC PERFORMANCE
1
Resolution (All Grades)
Integral Non-Linearity
(Relative Accuracy)
J, A, S
K, B, T
Differential Non-Linearity
J, A, S
K, B, T
Gain Error
J, A, S, K, B, T
Gain Temperature Coefficient
2
Power Supply Rejection Ratio
Output Leakage Current
DYNAMIC PERFORMANCE
Current Settling Time
2
AC Feedthrough at I
OUT12
REFERENCE INPUT
Input Resistance
DIGITAL INPUTS
3
Logical “1” Voltage
Logical “0” Voltage
Input Leakage Current
Input Capacitance
2
ANALOG OUTPUTS
Output Capacitance
2
Symbol
Min
Max
Units
Test Conditions/Comments
N
INL
12
12
Bits
LSB
Best Fit Straight Line Spec.
(Max INL – Min INL) / 2
+1
+1/2
DNL
+2
+1
+1
+1/2
LSB
+2
+1
Monotonicity
11 Bits Guaranteed
12 Bits Guaranteed
GE
TC
GE
PSRR
I
OUT
+12.3
+14.5
+2
LSB
ppm/°C
ppm/%
nA
Using Internal R
FB
∆Gain/∆Temperature
|∆Gain/∆V
DD
| ∆V
DD
= + 5%
+50
+10
+100
+200
R
L
=100Ω, C
L
=13pF
t
S
F
T
2.0
2.5
2.0
2.5
µs
mV p-p
Full Scale Change to 1/2 LSB
V
REF
= 10kHz, 20 Vp-p, sinewave
R
IN
5
10
20
5
20
kΩ
V
IH
V
IL
I
LKG
C
IN
3.0
0.8
+1
8
3.0
0.8
+1
8
V
V
µA
pF
C
OUT1
C
OUT1
C
OUT2
C
OUT2
POWER SUPPLY
Supply Voltage
5
Supply Current
V
DD
I
DD
+4.5
260
100
50
210
260
100
50
210
pF
pF
pF
pF
DAC Inputs all 1’s
DAC Inputs all 0’s
DAC Inputs all 1’s
DAC Inputs all 0’s
+5.5
2.5
+4.5
+5.5
2.5
V
mA
All digital inputs = 0 V or all = 5 V
Rev. 2.00
3
MP7542
ELECTRICAL CHARACTERISTICS (CONT’D)
Parameter
SWITCHING
CHARACTERISTICS
2, 4
WR Pulse Width
Address to WR Hold Time
CS to WR Hold Time
CLR Pulse Width
Byte Loading, CS to WR Setup
Byte Loading, Address to WR Setup
Byte Loading, WR to Data Setup
Byte Loading, WR to Data Hold
DAC Loading, CS to WR Setup
DAC Loading, Address to WR Setup
NOTES:
1
2
3
4
5
Symbol
Min
25
°
C
Typ
Max
Tmin to Tmax
Min
Max
Units
Test Conditions/Comments
t
WR
t
AWH
t
CWH
t
CLR
t
CWS1
t
AWS1
t
DS
t
DH
t
CWS2
t
AWS2
120
50
50
200
60
80
50
50
60
120
220
65
100
300
130
180
65
65
150
240
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Full Scale Range (FSR) is 10V for unipolar mode.
Guaranteed but not production tested.
Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur.
See timing diagram.
Specified values guarantee functionality. Refer to other parameters for accuracy.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C unless otherwise noted)
1, 2, 3
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Digital Input Voltage to GND (2) . GND –0.5 to V
DD
+0.5 V
I
OUT1
, I
OUT2
to GND . . . . . . . . . . . GND –0.5 to V
DD
+0.5 V
V
REF
to GND (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
V
RFB
to GND (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V
(Functionality Guaranteed +0.5 V)
Storage Temperature . . . . . . . . . . . . . . . . . –65
°
C to +150
°
C
Lead Temperature (Soldering, 10 seconds) . . . . . . +300
°
C
Package Power Dissipation Rating to 75
°
C
CDIP, PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . 700mW
Derates above 75
°
C . . . . . . . . . . . . . . . . . . . . . 10mW/
°
C
NOTES:
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies.
3
GND refers to AGND and DGND.
Rev. 2.00
4
MP7542
ADDRESS BUS VALID
A0 - A1
V
INH
V
INL
t
AWS1
CS
V
INH
V
INL
t
AWS2
WR
t
CWS1
t
AWH
t
CWH
t
WR
t
CWS2
DB3 - DB0
V
INH
V
INL
t
DS
t
DH
DATA
BUS VALID
Figure 1. Timing Diagram
MP7542 Control Inputs
A
1
X
X
0
0
0
0
1
1
1
1
A
0
X
X
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
CS
X
1
WR
X
1
0
CLR
0
1
1
1
1
1
1
1
1
1
Load 12-bit DAC register with data in LOW byte, MIDDLE
byte, & HIGH byte data registers
Load HIGH byte data register on edges as shown
Load MIDDLE byte data register on edges as shown
MP7542 Operation
Resets DAC 12-bit register to code 0000 0000 0000
No operation; device not selected
Load LOW byte data register on edges as shown
Load applicable
data register
with data at
D
0
- D
3
NOTES
1. 1 indicates logic HIGH
2. 0 indicates logic LOW
3. X indicates don’t care
4.
indicates LOW to HIGH transition
5. MSB XXXX XXXX XXXX LSB
high
middle low
byte
byte
byte
6. Although positive-going edge of either CS or WR will load data register, timing is optimized by using WR to
latch data and using CS as a device enable.
Table 1. Truth Table
Rev. 2.00
5
MCU
京公网安备 11010802033920号
EEWORLD
