Enhanced
Features
s
s
s
Memory Systems Inc.
DM2202/2212 EDRAM
1Mb x 4 Enhanced Dynamic RAM
Product Specification
2Kbit SRAM Cache Memory for 12ns Random Reads Within a Page
Fast 4Mbit DRAM Array for 30ns Access to Any New Page
Write Posting Register for 12ns Random Writes and Burst Writes
Within a Page (Hit or Miss)
s
256-byte Wide DRAM to SRAM Bus for 14.2 Gigabytes/Sec Cache
Fill
s
On-chip Cache Hit/Miss Comparators Maintain Cache Coherency
on Writes
s
s
s
s
s
s
s
Hidden Precharge and Refresh Cycles
Write-per-bit Option (DM2212) for Parity and Video Applications
Extended 64ms Refresh Period for Low Standby Power
300 Mil Plastic SOJ and TSOP-II Package Options
+5 and +3.3 Volt Power Supply Voltage Options
Low Power, Self Refresh Mode Option
Industrial Temperature Range Option
Description
The 4Mb Enhanced DRAM (EDRAM) combines raw speed with
innovative architecture to offer the optimum cost-performance solution
for high performance local or system main memory. In most high
speed applications, no-wait-state performance can be achieved without
secondary SRAM cache and without interleaving main memory banks at
system clock speeds through 50MHz. Two-way interleave will allow no-
wait-state operation at clock speeds greater than 100MHz without the
need of secondary SRAM cache. The EDRAM outperforms conventional
SRAM cache plus DRAM memory systems by minimizing processor wait
states for all possible bus events, not just cache hits. The combination
of data and address latching, 2K of fast on-chip SRAM cache, and
simplified on-chip cache control allows system level flexibility,
performance, and overall memory cost reduction not available with any
other high density memory component. Architectural similarity with
JEDEC DRAMs allows a single memory controller design to support
either slow JEDEC DRAMs or high speed EDRAMs. A system designed in
this manner can provide a simple upgrade path to higher system
performance.
Architecture
The EDRAM architecture has a simple integrated SRAM cache
which allows it to operate much like a page mode or static column
DRAM.
The EDRAM’s SRAM cache is integrated into the DRAM array as
tightly coupled row registers. Memory reads always occur from the
cache row register. When the internal comparator detects a page hit,
only the SRAM is accessed and data is available in 12ns from column
address. When a page read miss is detected, the new DRAM row is
loaded into the cache and data is available at the output all within
30ns from row enable. Subsequent reads within the page (burst reads
or random reads) can continue at 12ns cycle time. Since reads occur
from the SRAM cache, the DRAM precharge can occur simultaneously
without degrading performance. The on-chip refresh counter with
independent refresh bus allows the EDRAM to be refreshed during
cache reads.
Memory writes are internally posted in 12ns and directed to the
DRAM array. During a write hit, the on-chip address comparator
activates a parallel write path to the SRAM cache to maintain
Functional Diagram
A
0-8
Column Decoder
TSOP-II Pin
Configuration
Column
Add
Latch
11 Bit
Comp
Sense Amps
& Column Write Select
/G
I/O
Control
and
Data
Latches
DQ
0-3
/S
Row Decoder
Memory
Array
(2048 X 512 X 4)
/WE
NC
A
0
NC
A
1
NC
A
3
A
4
NC
A
5
/RE
V
CC
V
SS
V
SS
A
6
A
7
A
8
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS *
V
SS
V
SS
DQ
0
DQ
1
DQ
2
NC
DQ
3
/G
V
CC
V
CC
V
SS
V
SS
/WE
/S
/F
NC
W/R
NC
/CAL
A
10
NC
SOJ Pin
Configuration
/CAL
512 X 4 Cache (Row Register)
A
0
A
1
A
3
A
4
A
5
/RE
V
CC
V
SS
A
6
A
7
A
8
A
2
A
9
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
SS
DQ
0
DQ
1
DQ
2
DQ
3
/G
V
CC
V
SS
/WE
/S
/F
W/R
/CAL
A
10
A
0-10
Last
Row
Read
Add
Latch
Row
Add
Latch
/F
W/R
/RE
A
0-9
Row Add
and
Refresh
Control
Refresh
Counter
V
CC
V
SS
A
2
NC
A
9
V
CC
V
CC*
* Reserved for future use
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product without notice.
© 1996 Enhanced Memory Systems Inc.,
1850 Ramtron Drive, Colorado Springs, CO
Telephone
(800) 545-DRAM;
Fax
(719) 488-9095; http://www.csn.net/ramtron/enhanced
80921
38-2107-002
coherency. The EDRAM delivers 12ns cycle page mode memory
writes. Memory writes do not affect the contents of the cache row
register except during a cache hit.
By integrating the SRAM cache as row registers in the DRAM
array and keeping the on-chip control simple, the EDRAM is able
to provide superior performance over standard slow 4Mb DRAMs.
By eliminating the need for SRAMs and cache controllers, system
cost, board space, and power can all be reduced.
providing new column addresses to the multiplex address inputs.
New data is available at the output at time t
AC
after each column
address change. During read cycles, it is possible to operate in
either static column mode with /CAL=high or page mode with /CAL
clocked to latch the column address. In page mode, data valid
time is determined by either t
AC
or t
CQV
.
DRAM Read Miss
A DRAM read request is initiated by clocking /RE with W/R low
and /F & /CAL high. The EDRAM compares the new row address to
Functional Description
the LRR address latch (an 11-bit latch loaded on each /RE active
The EDRAM is designed to provide optimum memory
read miss cycle). If the row address does not match the LRR, the
requested data is not in SRAM cache and a new row must be
performance with high speed microprocessors. As a result, it is
fetched from the DRAM. The EDRAM will load the new row data
possible to perform simultaneous operations to the DRAM and
SRAM cache sections of the EDRAM. This feature allows the EDRAM into the SRAM cache and update the LRR latch. The data at the
to hide precharge and refresh operation during SRAM cache reads specified column address is available at the output pins at the
greater of times t
RAC
, t
AC
, and t
GQV
. It is possible to bring /RE high
and maximize SRAM cache hit rate by maintaining valid cache
after time t
RE
since the new row data is safely latched into SRAM
contents during write operations even if data is written to another
memory page. These new functions, in conjunction with the faster cache. This allows the EDRAM to precharge the DRAM array while
basic DRAM and cache speeds of the EDRAM, minimize processor data is accessed from SRAM cache. It is possible to access additional
SRAM cache locations by providing new column addresses to the
wait states.
multiplex address inputs. New data is available at the output at time
t
AC
after each column address change. During read cycles, it is
EDRAM Basic Operating Modes
possible to operate in either static column mode with /CAL=high or
The EDRAM operating modes are specified in the table below. page mode with /CAL clocked to latch the column address. In page
Hit and Miss Terminology
mode, data valid time is determined by either t
AC
or t
CQV
.
In this datasheet, “hit” and “miss” always refer to a hit or miss
DRAM Write Hit
to the page of data contained in the SRAM cache row register. This
If a DRAM write request is initiated by clocking /RE while W/R,
is always equal to the contents of the last row that was read from
(as modified by any write hit data). Writing to a new page does not /CAL, /WE, and /F are high, the EDRAM will compare the new row
address to the LRR address latch (an 11-bit address latch loaded
cause the cache to be modified.
on each /RE active read miss cycle). If the row address matches,
DRAM Read Hit
the EDRAM will write data to both the DRAM array and selected
A DRAM read request is initiated by clocking /RE with W/R low SRAM cache simultaneously to maintain coherency. The write
and /F & /CAL high. The EDRAM compares the new row address to address and data are posted to the DRAM as soon as the column
the last row read address latch (LRR - an 11-bit latch loaded on
address is latched by bringing /CAL low and the write data is
each /RE active read miss cycle). If the row address matches the
latched by bringing /WE low. The write address and data can be
latched very quickly after the fall of /RE (t
RAH
+ t
ASC
for the column
LRR, the requested data is already in the SRAM cache and no
address and t
DS
for the data). During a write burst sequence, the
DRAM memory reference is initiated. The data specified by the
second write data can be posted at time t
RSW
after /RE. Subsequent
column address is available at the output pins at the greater of
writes within a page can occur with write cycle time t
PC
. With /G
times t
AC
or t
GQV
. Since no DRAM activity is initiated, /RE can be
brought high after time t
RE1
, and a shorter precharge time, t
RP1
, is enabled and /WE disabled, it is possible to perform cache read
allowed. It is possible to access additional SRAM cache locations by operations while the /RE is activated in write hit mode. This allows
EDRAM Basic Operating Modes
Function
Read Hit
Read Miss
Write Hit
Write Miss
Internal Refresh
Low Power Standby
Unallowed Mode
Low Power Self-Refresh
Option
/S
L
L
L
L
X
H
H
H
/RE
↓
↓
↓
↓
↓
H
L
↓
W/R
L
L
H
H
X
X
X
H
/F
H
H
H
H
L
X
H
H
/CAL
H
H
H
H
X
H
X
L
/WE
X
X
H
H
X
H
X
H
A
0-10
Row = LRR
Row
≠
LRR
Row = LRR
Row
≠
LRR
X
X
X
X
Comment
No DRAM Reference, Data in Cache
DRAM Row to Cache
Write to DRAM and Cache, Reads Enabled
Write to DRAM, Cache Not Updated, Reads Disabled
Cache Reads Enabled
1mA Standby Current
Unallowed Mode (Except -L Option)
Standby Current, Internal Refresh Clock (-L Option)
H = High; L = Low; X = Don’t Care;
↓
= High-to-Low Transition; LRR = Last Row Read
1-20
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the row address supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle.
Low Power Mode
DRAM Write Miss
The EDRAM enters its low power mode when /S is high. In this
If a DRAM write request is initiated by clocking /RE while W/R,
mode, the internal DRAM circuitry is powered down to reduce
/CAL, /WE, and /F are high, the EDRAM will compare the new row standby current to 1mA.
address to the LRR address latch (an 11-bit latch loaded on each
/RE active read miss cycle). If the row address does not match, the
Low Power, Self-Refresh Option
When the low power, self refresh mode option is specified when
EDRAM will write data to the DRAM array only and contents of the
ordering the EDRAM, the EDRAM enters this mode when /RE is
current cache are not modified. The write address and data are
clocked while /S, W/R, /F, and /WE are high; and /CAL is low. In this
posted to the DRAM as soon as the column address is latched by
mode, the power is turned off to all I/O pins except /RE to minimize
bringing /CAL low and the write data is latched by bringing /WE
chip power, and an on-board refresh clock is enabled to perform self-
low. The write address and data can be latched very quickly after
refresh cycles using the on-board refresh counter. The EDRAM
the fall of /RE (t
RAH
+ t
ASC
for the column address and t
DS
for the
remains in this low power mode until /RE is brought high again to
data). During a write burst sequence, the second write data can be terminate the mode. The EDRAM /RE input must remain high for t
RP2
posted at time t
RSW
after /RE. Subsequent writes within a page can
following exit from self-refresh mode to allow any on-going internal
occur with write cycle time t
PC
. During a write miss sequence,
refresh to terminate prior to the next memory operation.
cache reads are inhibited and the output buffers are disabled
Write-Per-Bit Operation
(independently of /G) until time t
WRR
after /RE goes high. At the
The DM2212 version of the 1Mb x 4 EDRAM offers a write-per-
end of a write sequence (after /CAL and /WE are brought high and
bit capability which allows single bits of the memory to be selectively
t
RE
is satisfied), /RE can be brought high to precharge the memory.
written without altering other bits in the same word. This capability
It is possible to perform cache reads concurrently with the
may be useful for implementing parity or masking data in video
precharge. During write sequences, a write operation is not
graphics applications. The bits to be written are determined by a
performed unless both /CAL and /WE are low. As a result, /CAL can bit mask data word which is placed on the I/O data pins DQ prior
0-3
be used as a byte write select in multi-chip systems. If /CAL is not
to clocking /RE. The logic one bits in the mask data select the bits
clocked on a write sequence, the memory will perform a /RE only to be written. As soon as the mask is latched by /RE, the mask data
refresh to the selected row and data will remain unmodified.
is removed and write data can be placed on the databus. The mask
is only specified on the /RE transition. During page mode burst
/RE Inactive Operation
write operations, the same mask is used for all write operations.
It is possible to read data from the SRAM cache without clocking
+3.3 Volt Power Supply Operation
/RE. This option is desirable when the external control logic is
If the +3.3 volt power supply option is specified, the EDRAM
capable of fast hit/miss comparison. In this case, the controller can
avoid the time required to perform row/column multiplexing on hit will operate from a +3.3 volt ±0.3 volt power supply and all inputs
and outputs will have LVTTL/LVCMOS compatible signal levels. The
cycles. This capability also allows the EDRAM to perform cache
+3.3 volt EDRAM will not accept input levels which exceed the
read operations during precharge and refresh cycles to minimize
power supply voltage. If mixed I/O levels are expected in your
wait states and reduce power. It is only necessary to select /S and
system, please specify the +5 volt version of the EDRAM.
/G and provide the appropriate column address to read data as
shown in the table below. The row address of the SRAM cache
/CAL Before /RE Refresh (“/CAS Before /RAS”)
/CAL before /RE refresh, a special case of internal refresh, is
accessed without clocking /RE will be specified by the LRR address
discussed in the “Reduced Pin Count Operation” section below.
latch loaded during the last /RE active read cycle. To perform a
cache read in static column mode, /CAL is held high, and the cache
/RE Only Refresh Operation
contents at the specified column address will be valid at time t
AC
Although /F refresh using the internal refresh counter is the
after address is stable. To perform a cache read in page mode,
recommended method of EDRAM refresh, it is possible to perform
an /RE only refresh using an externally supplied row address. /RE
refresh is performed by executing a
write cycle
(W/R and /F are
Function
/S
/G
/CAL
A
0-8
high) where /CAL is not clocked. This is necessary so that the current
Cache Read (Static Column)
L
L
H
Column Address
cache contents and LRR are not modified by the refresh operation.
↓
All combinations of addresses A
0-9
must be sequenced every 64ms
Cache Read (Page Mode)
L
L
Column Address
refresh period. A
10
does not need to be cycled. Read refresh cycles
H = High; L = Low; X = Don’t Care;
↓
= Transitioning
1-21
read-modify-write, write-verify, or random read-write sequences
within the page with 12ns cycle times (the first read cannot
complete until after time t
RAC2
). At the end of a write sequence
(after /CAL and /WE are brought high and t
RE
is satisfied), /RE can
be brought high to precharge the memory. It is possible to perform
cache reads concurrently with precharge. During write sequences,
a write operation is not performed unless both /CAL and /WE are
low. As a result, the /CAL input can be used as a byte write select in
multi-chip systems. If /CAL is not clocked on a write sequence, the
memory will perform a /RE only refresh to the selected row and
data will remain unmodified.
/CAL is clocked to latch the column address. The cache data is
valid at time t
AC
after the column address is setup to /CAL.
are not allowed because a DRAM refresh cycle does not occur when
a read refresh address matches the LRR address latch.
Initialization Cycles
A minimum of 10 initialization (start-up) cycles are required
before normal operation is guaranteed. At least eight /F refresh
cycles and two read cycles to different row addresses are necessary
to complete initialization. /RE must be high for at least 300ns prior
to initialization.
Unallowed Mode
Read, write, or /RE only refresh operations must not be
performed to unselected memory banks by clocking /RE when /S is
high.
Reduced Pin Count Operation
Although it is desirable to use all EDRAM control pins to
optimize system performance, it is possible to simplify the interface
to the EDRAM by either tying pins to ground or by tying one or
more control inputs together. The /S input can be tied to ground if
the low power standby modes are not required. The /CAL and /F
pins can be tied together if hidden refresh operation is not
required. In this case, a CBR refresh (/CAL before /RE) can be
performed by holding the combined input low prior to /RE. A CBR
refresh does not require that a row address be supplied when /RE
is asserted. The timing is identical to /F refresh cycle timing. The
/WE input can be tied to /CAL if independent posting of column
addresses and data are not required during write operations. In
this case, both column address and write data will be latched by
the combined input during writes. W/R and /G can be tied together
if reads are not performed during write hit cycles. If these
techniques are used, the EDRAM will require only three control
lines for operation (/RE, /CAS [combined /CAL, /F, and /WE], and
W/R [combined W/R and /G]). The simplified control interface still
allows the fast page read/write cycle times, fast random read/write
times, and hidden precharge functions available with the EDRAM.
Pin Descriptions
/RE — Row Enable
This input is used to initiate DRAM read and write operations
and latch a row address. It is not necessary to clock /RE to read
data from the EDRAM SRAM row registers. On read operations, /RE
can be brought high as soon as data is loaded into cache to allow
early precharge.
Pin Names
Pin Names
A
0-10
/RE
DQ
0-3
/CAL
W/R
V
CC
Address Inputs
Row Enable
Data In/Data Out
Column Address Latch
Write/Read Control
Power (+5V or +3.3V)
/CAL — Column Address Latch
This input is used to latch the column address and in combination
with /WE to trigger write operations. When /CAL is high, the column
address latch is transparent. When /CAL is low, the column address
latch is closed and the output of the latch contains the address
present while /CAL was high.
W/R — Write/Read
This input along with /F specifies the type of DRAM operation
initiated on the low going edge of /RE. When /F is high, W/R
specifies either a write (logic high) or read operation (logic low).
/F — Refresh
This input will initiate a DRAM refresh operation using the
internal refresh counter as an address source when it is low on the
low going edge of /RE.
/WE — Write Enable
This input controls the latching of write data on the input data
pins. A write operation is initiated when both /CAL and /WE are low.
/G — Output Enable
This input controls the gating of read data to the output data
pins during read operations.
/S — Chip Select
This input is used to power up the I/O and clock circuitry.
When /S is high, the EDRAM remains in its low power mode. /S
must remain active throughout any read or write operation. With
the exception of /F refresh cycles, /RE should never be clocked
when /S is inactive.
DQ
0-3
— Data Input/Output
These bidirectional data pins are used to read and write data
to the EDRAM. On the DM2212 write-per-bit memory, these pins
are also used to specify the bit mask used during write operations.
A
0-10
— Multiplex Address
These inputs are used to specify the row and column
addresses of the EDRAM data. The 11-bit row address is latched on
the falling edge of /RE. The 9-bit column address can be specified
at any other time to select read data from the SRAM cache or to
specify the write column address during write cycles.
V
CC
Power Supply
These inputs are connected to the +5 or +3.3 volt power supply.
V
SS
Ground
These inputs are connected to the power supply ground
connection.
Function
Pin Names
V
SS
/WE
/G
/F
/S
NC
Ground
Write Enable
Output Enable
Refresh Control
Function
Chip Select - Active/Standby Control
Not Connected
1-22
AC Test Load and Waveforms
Load Circuit
+ 5.0 (+3.3 Volt Option)
R1 = 828Ω
R1 = 1178Ω
(5.0 volt)
(3.3 Volt Option)
CL = 50pf
VIL
≤5ns
V
IN
Timing Reference Point at V
IL
and V
IH
Input Waveforms
VIH
VIH
Output
R2 = 295Ω (5.0 volt)
R2 = 868Ω (3.3 Volt Option)
GND
VIL
≤5ns
Absolute Maximum Ratings
(Beyond Which Permanent Damage Could Result)
Capacitance
3.3V Option
Rating
- .5 ~ 4.6v
- .5 ~ 4.6v
- .5 ~ 4.6v
-40 ~ +85°C
-55 ~ 150°C
Class 1
20mA*
Description
Ratings
- 1 ~ 7v
- 1 ~ 7v
- 1 ~ 7v
-40 ~ +85°C
-55 ~ 150°C
Class 1
50mA*
Max
6pf
7pf
2pf
6pf
A0-10
Pins
Description
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Power Supply Voltage (V
CC
)
Ambient Operating Temperature (T
A
)
Storage Temperature (T
S
)
Static Discharge Voltage
(Per MIL-STD-883 Method 3015)
Short Circuit O/P Current (I
OUT
)
*One output at a time; short duration.
Input Capacitance
Input Capacitance
Input Capacitance
I/O Capacitance
/CAL, /RE, W/R, /WE, /F, /S
/G
DQ
0-3
Electrical Characteristics
Symbol
V
CC
V
IH
V
IL
V
OH
V
OL
I
i(L)
I
O(L)
T
A
= 0 to 70°C (Commercial), -40 to 85°C (Industrial)
Parameters
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Level
Output Low Level
Input Leakage Current
Output Leakage Current
L Option
Min
3.0V
2.0V
Vss-0.3V
2.4V
0.4V
-5µA
-5µA
5µA
5µA
Min
4.75V
2.4V
Vss-0.5V
2.4V
Max
5.25V
Vcc+0.5V
0.8V
Test Conditions
All Voltages Referenced to V
SS
Max
3.6V
V
CC
+0.3V
0.8V
I
OUT
= - 5mA (-2ma For 3.3 Volt Option)
0.4V
I
OUT
= 4.2mA (2ma For 3.3 Volt Option)
OV
≤
V
IN
≤
Vcc to 0.5 Volt
O
≤
V
I/O
≤
Vcc
-10µA
-10µA
10µA
10µA
Symbol
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
CC7
I
CCT
Operating Current
Random Read
Fast Page Mode Read
Static Column Read
Random Write
Fast Page Mode Write
Standby
Self-Refresh
(-L Option)
Average Typical
Operating Current
33MHz Typ
(1)
110mA
65mA
55mA
135mA
50mA
1mA
200 µA
-12 Max
225mA
145mA
110mA
190mA
135mA
1mA
200 µA
-15 Max
180mA
115mA
90mA
150mA
105mA
1mA
200 µA
Test Condition
/RE, /CAL, and Addresses Cycling: t
C
= t
C
Minimum
/CAL and Addresses Cycling: t
PC
= t
PC
Minimum
Addresses Cycling: t
SC
= t
SC
Minimum
/RE, /CAL, /WE, and Addresses Cycling: t
C
= t
C
Minimum
/CAL, /WE, and Addresses Cycling: t
PC
= t
PC
Minimum
All Control Inputs Stable
≥
V
CC
- 0.2V, Output Driven
/S, /F, W/R, /WE, and A
0-10
at
≥
V
CC
- 0.2V
/RE and /CAL at
≤
V
SS
+ 0.2V, I/O Open
See “Estimating EDRAM Operating Power”
Application Note
Notes
2, 3, 5
2, 4, 5
2, 4, 5
2, 3
2, 4
30mA
—
—
1
(1) “33MHz Typ” refers to worst case I
CC
expected in a system operating with a 33MHz memory bus. See power applications note for further details. This parameter is not 100% tested
or guaranteed. (2) I
CC
is dependent on cycle rates and is measured with CMOS levels and the outputs open. (3) I
CC
is measured with a maximum of one address change while
/RE = V
IL
. (4) I
CC
is measured with a maximum of one address change while /CAL = V
IH
. (5) /G is high.
1-23
京公网安备 11010802033920号
EEWORLD
