Data Sheet
January 2002
DSP1627 Digital Signal Processor
1 Features
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Supported by DSP1627 software and hardware devel-
opment tools.
Optimized for mobile communications applications
with a bit manipulation unit for higher coding efficiency.
On-chip, programmable, PLL clock synthesizer.
14 ns and 11 ns instruction cycle times at 5 V, 10 ns in-
struction cycle time at 3.0 V, and 20 ns and 12.5 ns in-
struction cycle times at 2.7 V.
Mask-programmable memory map option: the
DSP1627x36 features 36 Kwords on-chip ROM. The
DSP1627x32 features 32 Kwords on-chip ROM and
access to 16 Kwords external ROM in the same map.
Both feature 6 Kwords on-chip, dual-port RAM, and a
secure option for on-chip ROM.
Low power consumption:
— <5.5 mW/MIPS typical at 5 V.
— <1.5 mW/MIPS typical at 2.7 V.
Flexible power management modes:
— Standard sleep: 0.5 mW/MIPS at 5 V.
0.12 mW/MIPS at 2.7 V.
— Sleep with slow internal clock: 1.4 mW at 5 V.
0.4 mW at 2.7 V.
— Hardware STOP (pin halts DSP): <20
µA.
Mask-programmable clock options: crystal oscillator,
small signal, and CMOS.
Low-profile TQFP package (1.5 mm) available, provid-
ing excellent second-level reliability.
Sequenced accesses to X and Y external memory.
Object code compatible with the DSP1629.
Single-cycle squaring.
16 x 16-bit multiplication and 36-bit accumulation in
one instruction cycle.
Instruction cache for high-speed, program-efficient,
zero-overhead looping.
Dual 25 Mbits/s serial I/O ports with multiprocessor ca-
pability—16-bit data channel, 8-bit protocol channel.
8-bit parallel host interface:
— Supports 8-bit or 16-bit transfers.
—
Motorola
®
or
Intel
®
compatible.
8-bit control I/O interface.
256 memory-mapped I/O ports.
2 Description
The DSP1627 is Agere Systems Inc.’s first digital signal
processor offering 100 MIPS operation at 3.0 V and
80 MIPS operation at 2.7 V, with a reduction in power
consumption. Designed specifically for applications re-
quiring low power dissipation in mobile communications
systems, the DSP1627 is a signal-coding device that can
be programmed to perform a wide variety of fixed-point
signal processing functions. The device is based on the
DSP1600 core with a bit manipulation unit for enhanced
signal coding efficiency. The DSP1627 includes a mix of
peripherals specifically intended to support processing-
intensive but cost-sensitive applications in the area of
digital wireless communications.
The DSP1627x36 contains 36 Kwords of internal ROM
(IROM), but it doesn’t support the use of IROM and exter-
nal ROM (EROM) in the same memory map. The
DSP1627x32 supports the use of 32 Kwords of IROM
with 16 Kwords of EROM in the same map. Both devices
contain 6 Kwords of dual-port RAM (DPRAM), which al-
lows simultaneous access to two RAM locations in a sin-
gle instruction cycle.
The DSP1627 is object code compatible with the
DSP1617, while providing more memory and architectur-
al enhancements, including an on-chip clock synthesizer
and an 8-bit parallel host interface for hardware flexibility.
The DSP1627 supports 2.7 V, 3.0 V, and 5 V operation
and features flexible power management modes. Several
control mechanisms achieve low-power operation, in-
cluding a STOP pin for placing the DSP into a fully static,
halted state, and a programmable power control register
used to power down unused on-chip I/O units. These
power management modes allow for trade-offs between
power reduction and wake-up latency requirements. Dur-
ing system standby, power consumption is reduced to
less than 20
µA.
The on-chip clock synthesizer can be driven by an exter-
nal clock whose frequency is a fraction of the instruction
rate.
The device is packaged in a 100-pin BQFP or a 100-pin
TQFP and is available with 14 ns and 11 ns instruction
cycle times at 5 V, 10 ns instruction cycle times at 3.0 V,
and 20 ns and 12.5 ns instruction cycle times at 2.7 V.
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
IEEE
®
P1149.1 test port (JTAG boundary scan).
Full-speed in-circuit emulation hardware development
system on-chip.
DSP1627 Digital Signal Processor
Data Sheet
January 2002
Table of Contents
Contents
1
2
3
4
Page
Contents
Page
Features.............................................................. 1
Description .......................................................... 1
Pin Information.................................................... 3
Hardware Architecture ........................................ 7
4.1
DSP1627 Architectural Overview ............. 7
4.2
DSP1600 Core Architectural Overview .. 10
4.3
Interrupts and Trap ................................. 11
4.4
Memory Maps and Wait-States .............. 16
4.5
External Memory Interface (EMI)............ 18
4.6
Bit Manipulation Unit (BMU) ................... 19
4.7
Serial I/O Units (SIOs) ............................ 19
4.8
Parallel Host Interface (PHIF)................. 22
4.9
Bit Input/Output Unit (BIO)...................... 23
4.10 Timer ...................................................... 23
4.11 JTAG Test Port....................................... 24
4.12 Clock Synthesis ...................................... 26
4.13 Power Management ............................... 29
5 Software Architecture ....................................... 36
5.1
Instruction Set......................................... 36
5.2
Register Settings .................................... 45
5.3
Instruction Set Formats .......................... 55
6 Signal Descriptions ........................................... 61
6.1
System Interface..................................... 61
6.2
External Memory Interface ..................... 63
6.3
Serial Interface #1 .................................. 64
6.4
Parallel Host Interface or Serial Interface
#2 and Control I/O Interface ................... 65
6.5
Control I/O Interface ............................... 65
6.6
JTAG Test Interface ............................... 66
7 Mask-Programmable Options ........................... 67
7.1
Input Clock Options ................................ 67
7.2
Memory Map Options ............................. 67
7.3
ROM Security Options............................ 67
8 Device Characteristics ...................................... 68
8.1
Absolute Maximum Ratings.................... 68
8.2
Handling Precautions ............................. 68
8.3
Recommended Operating Conditions .... 68
8.4
Package Thermal Considerations .......... 69
9 Electrical Characteristics and Requirements .... 70
9.1
Power Dissipation................................... 73
10 Timing Characteristics for 5.0 V Operation ....... 75
10.1 DSP Clock Generation (5.0 V
Operation)............................................... 76
10.2 Reset Circuit (5.0 V Operation) .............. 77
10.3 Reset Synchronization (5.0 V
Operation)............................................... 78
10.4 JTAG I/O Specifications (5.0 V
Operation)............................................... 79
10.5 Interrupt (5.0 V Operation)...................... 80
10.6 Bit Input/Output (BIO) (5.0 V Operation) 81
10.7 External Memory Interface (5.0 V
Operation)............................................... 82
10.8 PHIF Specifications (5.0 V Operation).... 86
2
11
12
13
14
10.9 Serial I/O Specifications (5.0 V
Operation)............................................... 92
10.10 Multiprocessor Communication (5.0 V
Operation)............................................... 97
Timing Characteristics for 3.0 V Operation ....... 98
11.1 DSP Clock Generation (3.0 V
Operation)............................................... 99
11.2 Reset Circuit (3.0 V Operation)............. 100
11.3 Reset Synchronization (3.0 V
Operation)............................................. 101
11.4 JTAG I/O Specifications (3.0 V
Operation)............................................. 102
11.5 Interrupt (3.0 V Operation).................... 103
11.6 Bit Input/Output (BIO) (3.0 V
Operation)............................................. 104
11.7 External Memory Interface (3.0 V
Operation)............................................. 105
11.8 PHIF Specifications (3.0 V Operation).. 109
11.9 Serial I/O Specifications (3.0 V
Operation)............................................. 115
11.10 Multiprocessor Communication
(3.0 V Operation) .................................. 120
Timing Characteristics for 2.7 V Operation ..... 121
12.1 DSP Clock Generation (2.7 V
Operation)............................................. 122
12.2 Reset Circuit (2.7 V Operation)............. 123
12.3 Reset Synchronization (2.7 V
Operation)............................................. 124
12.4 JTAG I/O Specifications (2.7 V
Operation)............................................. 125
12.5 Interrupt (2.7 V Operation).................... 126
12.6 Bit Input/Output (BIO) (2.7 V
Operation)............................................. 127
12.7 External Memory Interface (2.7 V
Operation)............................................. 128
12.8 PHIF Specifications (2.7 V Operation).. 132
12.9 Serial I/O Specifications (2.7 V
Operation)............................................. 138
12.10 Multiprocessor Communication
(2.7 V Operation) .................................. 143
Crystal Electrical Characteristics and
Requirements.................................................. 144
13.1 External Components for the Crystal
Oscillator............................................... 144
13.2 Power Dissipation ................................. 144
13.3 LC Network Design for Third Overtone
Crystal Circuits...................................... 147
13.4 Frequency Accuracy Considerations .... 149
Outline Diagrams ............................................ 152
14.1 100-Pin BQFP (Bumpered Quad
Flat Pack).............................................. 152
14.2 100-Pin TQFP (Thin Quad Flat Pack)... 153
Agere Systems Inc.
Data Sheet
January 2002
DSP1627 Digital Signal Processor
3 Pin Information
SYNC1
90
OBE1
IBF1
OCK1
DB10
DB11
DB12
DB13
DB14
DB15
OLD1
ICK1
ILD1
DB5
DB6
DB7
DB8
DB9
V
DD
V
DD
V
SS
DO1
91
V
SS
100
13
12
11
10
99
98
97
96
95
94
93
92
89
9
8
7
6
5
4
3
2
1
V
SS
DB4
DB3
DB2
DB1
DB0
IO
ERAMHI
V
DD
ERAMLO
EROM
RWN
V
SS
EXM
AB15
AB14
V
DD
AB13
AB12
AB11
AB10
AB9
AB8
AB7
V
SS
V
SS
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
DI1
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
V
DD
SADD1
DOEN1
OCK2/PCSN
DO2/PSTAT
SYNC2/PBSEL
ILD2/PIDS
OLD2/PODS
IBF2/PIBF
OBE2/POBE
ICK2/PB0
DI2/PB1
V
SS
DOEN2/PB2
SADD2/PB3
V
DD
IOBIT0/PB4
IOBIT1/PB5
IOBIT2/PB6
IOBIT3/PB7
VEC3/IOBIT4
VEC2/IOBIT5
VEC1/IOBIT6
VEC0/IOBIT7
V
SS
PIN #1
IDENTIFIER
ZONE
DSP1627
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
CKI
62
CKI2
V
DDA
V
SS
STOP
IACK
TRAP
RSTB
V
SSA
V
DD
AB6
AB5
AB4
AB3
AB2
AB1
AB0
INT1
INT0
CKO
V
DD
TDO
TCK
TMS
TDI
63
5-4218 (F).b
Figure 1. DSP1627 BQFP Pin Diagram
Agere Systems Inc.
3
DSP1627 Digital Signal Processor
Data Sheet
January 2002
3 Pin Information
(continued)
SYNC1
77
OCK1
OBE1
DB10
DB11
DB12
DB13
DB14
DB15
ICK1
OLD1
IBF1
ILD1
DB5
DB6
DB7
DB8
DB9
DO1
78
V
DD
V
DD
V
SS
V
SS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
76
V
SS
DI1
V
SS
DB4
DB3
DB2
DB1
DB0
IO
ERAMHI
V
DD
ERAMLO
EROM
RWN
V
SS
EXM
AB15
AB14
V
DD
AB13
AB12
AB11
AB10
AB9
AB8
AB7
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
DSP1627
63
62
61
60
59
58
57
56
55
54
53
52
51
V
DD
SADD1
DOEN1
OCK2/PCSN
DO2/PSTAT
SYNC2/PBSEL
ILD2/PIDS
OLD2/PODS
IBF2/PIBF
OBE2/POBE
ICK2/PB0
DI2/PB1
V
SS
DOEN2/PB2
SADD2/PB3
V
DD
IOBIT0/PB4
IOBIT1/PB5
IOBIT2/PB6
IOBIT3/PB7
VEC3/IOBIT4
VEC2/IOBIT5
VEC1/IOBIT6
VEC0/IOBIT7
V
SS
26
27
28
29
30
31
32
33
34
37
38
39
40
41
42
43
44
45
46
47
48
CKI
24
CKI2
35
36
RSTB
V
SS
V
DDA
TRAP
STOP
IACK
TMS
V
SSA
V
DD
V
DD
INT1
INT0
TCK
AB6
AB5
AB4
AB3
AB2
AB1
AB0
TDO
CKO
TDI
50
5-4219 (F).b
Figure 2. DSP1627 TQFP Pin Diagram
4
Agere Systems Inc.
Data Sheet
January 2002
DSP1627 Digital Signal Processor
3 Pin Information
(continued)
Functional descriptions of pins 1—100 are found in Section 6, Signal Descriptions. The functionality of pins 61 and
62 (TQFP pins 48 and 49) are mask-programmable (see Section 7, Mask-Programmable Options). Input levels on
all I and I/O type pins are designed to remain at full CMOS levels when not driven by the DSP.
Table 1. Pin Descriptions
BQFP Pin
1, 2, 3, 4,
5, 7, 8, 9,
10, 11, 12,
15, 16, 17,
18, 19
20
21
23
24
25
27
28, 29, 31,
32, 33, 34,
35, 36, 37,
40, 41, 42,
43, 44, 45,
46
47
48
50
51
52
53
54
56
57
58
59
TQFP Pin
88, 89, 90,
91, 92, 94,
95, 96, 97,
98, 99, 2,
3, 4, 5, 6
7
8
10
11
12
14
15, 16, 18,
19, 20, 21,
22, 23, 24,
27, 28, 29,
30, 31, 32,
33
34
35
37
38
39
40
41
43
44
45
46
Symbol
DB[15:0]
Type
Name/Function
I/O* External Memory Data Bus DB[15:0].
IO
ERAMHI
ERAMLO
EROM
RWN
EXM
AB[15:0]
O
†
O
†
O
†
O
†
O
†
I
O*
Data Address 0x4000 to 0x40FF I/O Enable.
Data Address 0x8000 to 0xFFFF External RAM Enable.
Data Address 0x4100 to 0x7FFF External RAM Enable.
Program Address External ROM Enable.
Read/Write Not.
External ROM Enable.
External Memory Address Bus 15—0.
INT1
INT0
IACK
STOP
TRAP
RSTB
CKO
TCK
TMS
TDO
TDI
I
I
O*
I
I/O*
I
O
†
I
I
‡
O
§
I
‡
Vectored Interrupt 1.
Vectored Interrupt 0.
Interrupt Acknowledge.
STOP Input Clock.
Nonmaskable Program Trap/Breakpoint Indication.
Reset Bar.
Processor Clock Output.
JTAG Text Clock.
JTAG Test Mode Select.
JTAG Test Data Output.
JTAG Test Data Input.
Mask-Programmable Input Clock Option
CMOS
Small
Crystal
Signal
Oscillator
CKI
V
AC
XLO, 10 pF capacitor to V
SS
V
SSA
V
CM
XHI, 10 pF capacitor to V
SS
Vectored Interrupt Indication 0/Status/Control Bit 7.
Vectored Interrupt Indication 1/Status/Control Bit 6.
Vectored Interrupt Indication 2/Status/Control Bit 5.
Vectored Interrupt Indication 3/Status/Control Bit 4.
61
62
65
66
67
68
48
49
52
53
54
55
CKI**
CKI2**
VEC0/IOBIT7
VEC1/IOBIT6
VEC2/IOBIT5
VEC3/IOBIT4
I
I
I/O*
I/O*
I/O*
I/O*
CMOS
CKI
Open
* 3-states when RSTB = 0, or by JTAG control.
† 3-states when RSTB = 0 and INT0 = 1. Output = 1 when RSTB = 0 and INT0 = 0, except CKO which is free-running.
‡ Pull-up devices on input.
§ 3-states by JTAG control.
** See Section 7, Mask-Programmable Options.
†† For SIO multiprocessor applications, add 5 kΩ external pull-up resistors to SADD1 and/or SADD2 for proper initialization.
Agere Systems Inc.
5
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