DTC-19300
LVDT/RVDT-TO-DIGITAL CONVERTER
DESCRIPTION
The DTC-19300 is a 12- or 14-bit
LVDT (Linear Variable Differential
Transformer)- or RVDT (Rotary
Variable Differential Transformer)-to-
digital converter which also supplies
the AC excitation to drive the LVDT.
Internal AC excitation voltage, fre-
quency, signal gain and resolution are
all programmable for optimum system
performance. Packaged in a 36-pin
hybrid, the DTC-19300 also features
Velocity (VEL) and Built-In-Test (BIT)
outputs. The three-state digital out-
puts are provided in a two byte for-
mat, for easy computer interface.
The DTC-19300 has been designed
precisely for use with an LVDT.
Inherent characteristics of the DTC-
19300, such as the input to output
phase shift, have been given con-
siderable attention. The converter’s
reference voltage is derived from,
and is in phase with, the LVDT out-
put signal. Therefore, any errors due
to the transducer’s phase shift are
virtually eliminated. Additionally, the
programmability of the DTC-19300
will accomodate a broad range of
LVDT’s.
FEATURES
•
Internal Oscillator:
Programmable for Voltage and
Frequency
•
Programmable Signal Gain
•
Programmable for 12- or 14-Bit
Resolution
APPLICATIONS
The DTC-19300 provides many fea-
tures previously supplied by individual
system components. Because of its
internal AC source, programmable
features, fault indicator (BIT), and
velocity output (VEL), the need for
other system circuits is minimized. The
DTC-19300 is an excellent choice for
applications using the LVDT transduc-
er for position feedback, such as mili-
tary, commercial aerospace and
industrial control systems.
•
Velocity Output
•
Built-In-Test Output
•
Three-State, Two-Byte
Digital Output
10k
R1
35
SO
10k
R5
PHASE
COMP
C2
29
SJ
DTC-19300
REFERENCE
CONDITIONER
BIT
DETECT
18
BIT
ZERO SET
TIMING
LVDT
FULL
SCALE
R2
26
34 SG
VEL
-
+
PROG
GAIN
AMP
DIFF
SIG
REF
HIGH
ACCURACY
RATIO BRIDGE
ERROR
AMP
DEMOD
1 LSB ANTILITTER
FEEDBACK
ERROR
PROCESSOR
VCO
U
T
33 S
32 R
25
DIF
GAIN
SUM
(REF)
14 BIT BRIDGE
TRANSPARENT
LATCH
U
14 BIT
U-D COUNTER
T
24
e
V
31 RO
36 RI
U/D
50 ns DELAY
23
A
C1
19 OSC
+
21
FREQ
R4 22
RM
AMPL
R3
20
1
EM
POWER
OSCILLATOR
14 BIT OUTPUT
TRANSPARENT
LATCH
INH
INHIBIT
Q
TRANSPARENT
LATCH
17
INH
30
POWER
SUPPLY
CONDITIONER
+5 V
3 STATE
TTL BUFFER
3 STATE
TTL BUFFER
INTERNAL
DC REF (11V)
27
+15 V
16
BITS 1-6
BITS 7-14
EL
FIGURE 1. DTC-19300 BLOCK DIAGRAM
©
1986, 1999 Data Device Corporation
TABLE 1. DTC-19300 SPECIFICATIONS
Specifications apply over temperature and power supply ranges.
PARAMETER
RESOLUTION
ACCURACY
REPEATABILITY
DIFFERENTIAL LINEARITY
FREQUENCY OUT
(OSC Pin 19)
Frequency
Voltage
Current Drive
Protection
REFERENCE IN (Rl)
Full Scale Voltage
Input Impedance
REFERENCE (R)
Voltage
Input Impedance
SIGNAL IN (S)
Full Scale Voltage
Input Impedance
DIGITAL INPUTS/OUTPUTS
Logic Type
Inputs
Loading
INH (Inhibit)
EM (Enable Bits 1-6)
EL (Enable Bits 7-14)
A (Resolution Control)
OUTPUTS
Parallel Data
BIT (Built in Test)
Drive Capability
VALUE
12 or 14 bits
0.25, 0.05% of Reading
1 LSB max
1 LSB max
5 kHz ±10%
2.7 Vrms ±20%
20 mA rms min
Short circuit, overcurrent, and voltage transient protected.
2 Vrms ±10%
20 MOhms min
1 Vrms ±10%
20 MOhms min
2 Vrms
20 MOhms min
Tunable down to 400 Hz; disable with R4 =
∞
(see Setting Up and Programming).
20% at room temp, add 20% at overtemp. Scalable down (see Setting Up and
Programming).
Programmable.
See Ordering Information
DESCRIPTION
Transient protected voltage follower.
Transient protected voltage follower.
Transient protected voltage follower.
TTL/CMOS compatible.
Logic 0 = 0.8 V max
Logic 1 = 2.0 V min
10 µA max
Pull-up current source to +5 V//5 pF, CMOS transient protected.
Logic
Logic
Logic
Logic
0
1
0
1
inhibits, data valid within 0.5 µs
enables.
enables, data valid within 150 ns.
= high impedance, data high Z within 100 ns.
Logic 1 = 14-bit resolution.
Logic 0 = 12-bit resolution.
12 or 14 bits
Bipolar two’s complement.
Bit 1 = MSB; Bit 14 or Bit 12 = LSB.
Logic 0 for BIT condition (converter malfunction).
1.6 mA at 0.4 V max +50 pF.
-0.4 mA at 2.8 V min +50 pF.
When in the third state.
Logic 0 = 1 TTL load
Logic 1 = 10 TTL loads
High Z = 10 µA//5 pF max
5.5 VDC nom
±4 V ±15%
200 PPM/°C max
2% max
2% of output max
10 mV max
50 mV rms
0.5% max
40 kOhms min
1 full range per sec, min
18 Hz
1600 1/sec
2
0.4 1/sec
4000 1/sec
40 1/sec
20 1/sec
0.1 full ranges per sec
2
150 ms
ANALOG OUTPUTS
V (Analog Ground)
VEL (Velocity)
Scaling
Scaling TC
Reversal Error
Linearity
Zero Offset
Noise and Ripple
AC peak/DC avg
Load
DYNAMIC CHARACTERISTICS
Tracking Rate
Bandwidth, Closed Loop
Ka
A1
A2
A
B
Acc for 1 LSB lag
Settling time - half scale step
VEL is with respect to V.
1 (14-bit) or 4 (12-bit) ranges per second.
2
TABLE 1. DTC-19300 SPECIFICATIONS (CONTD)
Specifications apply over temperature and power supply ranges.
PARAMETER
POWER SUPPLIES
+5V SUPPLY
Nominal Voltage and Range
Max Voltage w/o Damage
Current, Peak
Current, Average
+15V SUPPLY
Nominal Voltage and Range
Max Voltage w/o Damage
Current, Peak
Current, Average
TEMPERATURE RANGES
Operating, Ambient
-3XX
-1XX
Storage
PHYSICAL CHARACTERISTICS
Size
Weight
VALUE
DESCRIPTION
+5 VDC ±10%
+8 VDC
10 mA max
10 mA max
+15 VDC ±5%
+18 VDC
25 mA max, +√2 x Iosc rms.
35 mA max, + 0.9 x 0.5 x Iosc rms.
0°C to +70°C
-55°C to +125°C
-65°C to +150°C
0.78 x 1.9 x 0.21 inches
(20 x 48 x 5.3 mm)
1 oz
(28 gm)
36-pin DDIP
INTRODUCTION
The circuit shown in FIGURE 1 (DTC-19300 Block Diagram)
consists of four main parts:
1. signal input conditioner
2. feedback loop (whose elements include a high accuracy
ratio bridge, a demodulator, an error processor, a VCO and an
up-down counter)
3. power oscillator to excite the LVDT
4. digital interface circuit (including various latches and buffers)
In the LVDT, position output is transmitted as a differential volt-
age that varies linearly with changes in the core position. The
DTC-19300 receives the differential and sum voltage at its inputs
and internally produces a digital position
δ
which tracks the dif-
ferential position
λ
to within the specified accuracy of the con-
verter.
A high accuracy ratio bridge is used to compute (λ -
δ),
where:
λ
= the LVDT’s core position.
δ
= the digital position contained in the converter’s up-down
counter.
The tracking process consists of continually adjusting
δ
to make
(λ -
δ)
à
0, so that
δ
will represent the core’s position,
λ.
The ratio bridge output is fed to a demodulator whose output is
an analog DC level proportional to (λ -
δ).
The error processor
receives its input from the demodulator and integrates the error
signal (λ -
δ)
which then drives a Voltage-Controlled Oscillator
(VCO).
Functionally, the up-down counter is an incremental integrator.
Therefore, there are two stages of integration which make the
converter a type II tracking servo. In a type II servo the VCO
3
always settles to the counting rate which makes the dδ/dt equal
to dλ/dt without lag. The output data will always be fresh and
available as long as the maximum tracking rate of the converter
is not exceeded.
POWER OSCILLATOR
The DTC-19300 contains an internal power oscillator. The OSC
output (pin 19) can be programmed for voltage and frequency.
The default output voltage is 2.7 Vrms, scalable down with an
external resistor R3 connected between RM (pin 20) and V (pin
25). The default frequency is 5 kHz, tunable to 400 Hz with an
external resistor R4 connected between RF1 (pin 21) and RF2
(pin 22). If desired, an external oscillator can be used in place of
the internal oscillator.
SOLID STATE BUFFERED INPUTS
The signal and reference inputs are voltage follower inputs with
high impedance that do not load the LVDT. The maximum tran-
sient peak voltage should not exceed 100 V.
DIGITAL INTERFACE
The digital interface circuitry has three main functions:
1. latch the output bits during an Inhibit (INH) command allow-
ing stable data to be read out of the DTC-19300
2. furnish parallel tri-state data formats
3. act as a buffer between the internal CMOS logic and the
external TTL logic
In the DTC-19300, applying an INHIBIT (INH) command will lock
the data in the Output Transparent Latch without interfering with
the continuous tracking of the feedback loop. Therefore, the dig-
ital position always updates, and the INHIBIT can be applied for
an arbitrary amount of time. The Inhibit Transparent Latch and
the 50 ns delay are part of the Inhibit circuitry. For further infor-
mation, see the INHIBIT (INH, PIN 17) paragraph.
edge of T. An INH input, regardless of its duration, does not
affect the converter update.
A simple method of interfacing to a computer is:
1. apply INH
2. wait 0.5 µs minimum
3. transfer data and release INH
As long as the converter’s maximum tracking rate is not exceed-
ed, there will be no lag in the converter output. If a step input
occurs, as when power is initially applied, the response will be
critically damped. FIGURE 3 shows the response to a step input.
After initial slewing at the maximum tracking rate of the convert-
er, there is one overshoot (inherent in a type II servo). The over-
shoot settling to final value is a function of the small signal set-
tling to final value.
LOGIC OUTPUT
Logic outputs from the DTC-19300 consist of the LVDT core’s
digital position in 12 or 14 parallel data bits. All logic outputs are
short-circuit proof to ground and +5 V. The internal Timing signal
(T) is a positive, 0.4 to 0.7 µs pulse. Data changes approximate-
ly 50 ns after the leading edge of T, and the position is deter-
mined by the sum of the bits at logic 1. Digital outputs are three-
state and are provided in two bytes: bits 1 through 6 (MSBs)
which are enabled by the signal EM, and bits 7 through 14
(LSBs) which are enabled by the signal EL. Outputs are valid
(logic 1 or 0) 150 ns maximum after setting EM or EL low, and
are high impedance within 100 ns maximum of setting EM or EL
high. Both EM and EL are internally puIled-up to +5 V at 100 nA
maximum .
BUILT-IN-TEST (BIT, PIN 18)
INHIBIT (INH, PIN 17)
The INH input locks the Output Transparent Latch (See FIGURE
1) so the bits will remain stable while data is being transferred.
The output is stable 0.5 µs after INH is driven to logic 0.
A logic 0 applied to the T input latches data, and a logic 1 applied
to T allows the bits to change. The Inhibit Transparent Latch pre-
vents the transmission of invalid data when there is an overlap
between T (VCO clock to up-down counter) and INH. While the
counter is not being updated, T is at a logic 0 and the Inhibit
Latch is transparent. When T goes to a logic 1, the Inhibit Latch
is locked. If T occurs after INH has been applied, the latch will
remain locked and its data will not change until T returns to logic
0; if INH is applied during T, the latch will not lock until the T pulse
is a logic 0. The purpose of the 50 ns delay is to prevent a race
condition between T and INH where the up-down counter begins
to change as an INH is applied.
FIGURE 2 illustrates the Inhibit Timing. Whenever an input posi-
tion change occurs, the converter changes the digital position in
1 LSB steps and generates a T pulse, delayed by 50 ns, nomi-
nal. Valid data is available at the outputs 0.2 µs after the leading
The BIT output monitors the level of the demodulator (D). If D
exceeds approximately 65 bits, the logic level at BIT will change
from logic 1 to logic 0. This condition will occur during a large
step and reset after the converter settles out. BIT will also be set
for an over-velocity condition because the converter loop cannot
maintain input-output sync, or if the converter malfunctions
where it cannot maintain the loop at a null.
VELOCITY
OUT
ERROR PROCESSOR
+
-
CT
e
A
1
S + 1
B
S
S +1
10B
VCO
A
2
S
DIGITAL
POSITION
OUT (φ)
LVDT's POSITION
INPUT
H=1
CONVERTER
TRANSFER
FUNCTION
G=
A
2
S + 1
B
S
2
S +1
10B
WHERE:
A
2
= A
1
A
2
FIGURE 4.CONTROL LOOP BLOCK DIAGRAM
INH
DATA
,,,,,,
0.5 µs MAX
VALID
BW
B
A
ω
(rad/sec)
FIGURE 2. INHIBIT TIMING
OVERSHOOT
θ
2
FIGURE 5. OPEN LOOP BODE PLOT
VEL
(pin 26)
100k
OUTPUT
0.1 µF
RC = 1/A = 1/40
θ
1
SETTLING TIME
SMALL SIGNAL
SETTLING TIME
MAX SLOPE EQUALS
TRACKING RATE (SLEW RATE)
FIGURE 3. RESPONSE TO A STEP INPUT
FIGURE 6. VELOCITY FILTER
4
VELOCITY (VEL, PIN 26)
The Velocity output (VEL) from the DTC-19300 is a DC voltage
proportional to the angular velocity (dλ/dt = dδ/dt). The velocity is
input to the second integrator, as shown in FIGURE 4. Its linear-
ity is dependent solely on the linearity of the voltage controlled
oscillator (VCO). An open loop Bode plot is shown in FIGURE 5.
Bandwidth (BW) and the acceleration constant (Ka) can be
determined by the following formula:
Closed Loop Bandwidth (Hz) =
√
2 x A
π
Output VEL is not required for normal operation of the converter;
V is used as an internal DC reference. Maximum loading on V
and VEL is 40k.
The simple filter shown in FIGURE 6 will eliminate the one over-
shoot for a step velocity input and filter the carrier frequency rip-
ple from the velocity output.
Vosc = 0.8 volts x turns ratio
b. Calculate the value of R3 with the equation below:
R3 = Vosc x 100k
2.7 - Vosc
c. Calculate the value of the coupling capacitor C1 so that its
impedance will be less than 1/10 the impedance of the
LVDT at the operating frequency.
CONVERTER FULL SCALE
4. Calculate the value of R2 (full-scale setting resistor) with the
LVDT at full travel. This results in 1.6 Vrms between pin 35
(SO) and pin 25 (V). Use the following equation:
R2 =
10k x pin 33 (S) voltage
1.6 - pin 33 (S) voltage
ELECTRONIC LIMIT STOPS
The DTC-19300 incorporates electronic limit stops and will not
count up past +FS-1 LSB or down past -FS.
PHASE COMPENSATION
5. At full travel, monitor pin 24 (e) voltage with an oscilloscope
and determine the value for C2 that gives minimum output.
This value (of C2) can be used for all applications which use
the same LVDT.
OUTPUT CODING
TABLE 2 lists the digital output codes of the DTC-19300 for var-
ious positions of the LVDT, including full scale (FS) and half scale
(HS). TABLE 3 lists the weight of each bit with respect to the full
scale output.
TABLE 2. DIGITAL OUTPUT CODES
SCALE
+FS - 1 LSB
+HS
+1 LSB
ZERO
-1 LSB
-HS
-FS
(MSB)
DIGITAL OUTPUT
(LSB)
CONVERTER RESOLUTION
6. Select 12-bit or 14-bit operating mode. The 12-bit mode pro-
vides faster response to input variations and is set by ground-
ing pin 23 (A). The 14 bit mode provides higher resolution and
is set by connecting pin 18 (BIT output) to pin 23 (A).
In both modes, if the BIT line goes low indicating an error condition
(the error signal to error processor and VCO is too large), the DTC-
19300 is set to 12-bit mode so that the error can be driven to null
faster. Once this happens, the converter returns to the original setting.
Note: Consult factory for information concerning the use of the
converter with 2-wire LVDTs.
SJ
PHASE
COMP
C2
R5
10k
FULL
SCALE
R2
10k
R1
SO
29
0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0
35
SETTING UP AND PROGRAMMING THE DTC-19300
To set up and operate the DTC-19300, refer to FIGURE 7 and
proceed as follows:
TO V
(PIN 25)
SG
S
34
33
24
e
R
32
INTERNAL OSCILLATOR
1. Select the LVDT’s operating frequency.
2. Calculate the value of R4 (the oscillator frequency setting
resistor) by using the LVDT frequency in the equation below.
1.14 x 10
12
R4 (in Ohms) =
- 45.6k
(Frequency in Hz)
2
3. Calculate the value of R3 (the oscillator amplitude setting
resistor), to result in 0.8 Vrms between pin 32 (R) and pin 25
(V), when the LVDT is at its null position (core in the center).
This usually requires a 0.8 Vrms input to the LVDT primary.
Proceed as follows:
a. Use the LVDT turns ratio (usually 1:1) to calculate the
oscillator output with the following equation:
LVDT
V
RO
RI
C1
OSC
+
RF1
FREQ
R4
RF2
AMPL
R3
22
20
25
31
36
19
21
DTC-193000
A
23
18
BIT
TO V
(PIN 25)
RM
FIGURE 7. DTC-19300 SET-UP
5
Electronics Design Contest
京公网安备 11010802033920号
EEWORLD
