a
FEATURES
Low Input Offset Voltage: 75 V Max
Low Offset Voltage Drift, Over –55 C < T
A
< +125 C:
0.5 V/ C Max
Low Supply Current (Per Amplifier): 725 A Max
High Open-Loop Gain: 5000 V/mV Min
Low Input Bias Current: 2 nA Max
Low Noise Voltage Density: 11 nV/√Hz at 1 kHz
Stable with Large Capacitive Loads: 10 nF Typ
Pin Compatible to OP221, MC1458, and LT1013 with
Improved Performance
Available in Die Form
GENERAL DESCRIPTION
Dual Low Offset, Low Power
Operational Amplifier
OP200
PIN CONNECTIONS
16-Lead SOIC (S
-
Suffix)
–IN A
1
+IN A
2
NC
3
V–
4
NC
5
+IN B
6
+
16
OUT A
15
NC
14
NC
13
V+
12
NC
11
NC
10
OUT B
9
NC
NC
8
NC = NO CONNECT
The OP200 is the first monolithic dual operational amplifier to
offer OP77 type precision performance. Available in the industry-
standard 8-lead pinout, the OP200 combines precision performance
with the space and cost savings offered by a dual amplifier.
The OP200 features an extremely low input offset voltage of less
than 75
µV
with a drift below 0.5
µV/°C,
guaranteed over the full
military temperature range. Open-loop gain of the OP200 exceeds
5,000,000 into a 10 kΩ load; input bias current is under 2 nA;
CMR is over 120 dB and PSRR below 1.8
µV/V.
On-chip
Zener zap trimming is used to achieve the extremely low input
offset voltage of the OP200 and eliminates the need for offset
pulling.
Power consumption of the OP200 is very low, with each amplifier
drawing less than 725
µA
of supply current. The total current
drawn by the dual OP200 is less than one-half that of a single
OP07, yet the OP200 offers significant improvements over this
industry-standard op amp. The voltage noise density of the OP200,
11 nV/√Hz at 1 kHz, is half that of most competitive devices.
8-Lead PDIP (P-Suffix)
8-Lead CERDIP (Z-Suffix)
OUT A
1
–IN A
2
+IN A
3
V–
4
A
– +
B
+ –
8
7
6
5
The OP200 is pin compatible with the OP221, LM158,
MC1458/1558, and LT1013.
The OP200 is an ideal choice for applications requiring multiple
precision op amps and where low power consumption is critical.
For a quad precision op amp, see the OP400.
V+
BIAS
VOLTAGE
LIMITING
NETWORK
+IN
–IN
REV. B
Figure 1. Simplified Schematic (One of two amplifiers is shown.)
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2004 Analog Devices, Inc. All rights reserved.
–
–IN B
7
–
+
V+
OUT B
–IN B
+IN B
OUT
V–
OP200–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Input Offset Voltage
Long-Term Input
Voltage Stability
Input Offset Current
Input Bias Current
Input Noise Voltage
Input Noise
Voltage Density*
Input Noise Current
Input Noise
Current Density
Input Resistance
Differential Mode
Input Resistance
Common Mode
Large Signal
Voltage Gain
*Sample
tested.
Specifications subject to change without notice.
(V
S
=
±15
V, T
A
= 25 C, unless otherwise noted.)
Min
OP200A/E
Typ
Max
25
0.1
75
Min
OP200G
Typ
80
0.1
1.0
2.0
0.05
0.1
0.5
36
18
22
11
15
0.4
10
125
3000
1500
7000
3200
3.5
5.0
Max
200
Unit
µV
µV/mo
nA
nA
µV
p-p
nV/√Hz
pA
p-p
pA/√Hz
MΩ
GΩ
Symbol
V
OS
Conditions
I
OS
I
B
e
n p-p
e
n
i
n p-p
i
n
R
IN
R
INCM
A
VO
V
CM
= 0 V
V
CM
= 0 V
0.1 Hz to 10 Hz
f
O
= 10 Hz
f
O
= 1000 Hz
0.1 Hz to 10 Hz
f
O
= 10 Hz
0.05
0.1
0.5
22
11
15
0.4
10
125
V
O
–
±
10 V
R
L
= 10 kΩ
R
L
= 2 kΩ
5000
2000
12000
3700
M/mV
–2–
REV. B
OP200
ELECTRICAL CHARACTERISTICS
(V = 15 V, –55 C
≤
T
≤
+125 C for OP200A, unless otherwise noted.)
S
A
Parameter
Input Offset Voltage
Average Input Offset Voltage Drift
Input Offset Current
Input Bias Current
Large Signal Voltage Gain
Symbol
V
OS
TCV
OS
I
OS
I
B
A
VO
Conditions
Min
OP200A
Typ
45
0.2
Max
125
0.5
2.5
5.0
Unit
µV
µV/°C
nA
nA
V/mV
V/mV
V
dB
µV/V
V
V
V
CM
= 0 V
V
CM
= 0 V
V
O
= 10 V
R
L
= 10
Ω
R
L
= 2 kΩ
V
CM
=
±
12 V
V
S
= +3 V to +18 V
R
L
= 10 kΩ
R
L
= 2 kΩ
No Load
A
V
= 1
±
12
±
11
3000
1000
±
12
115
0.15
0.9
9000
2700
±
12.5
130
0.2
±
12.4
±
12
600
8
Input Voltage Range*
Common-Mode Rejection
Power Supply Rejection Ratio
Output Voltage Swing
Supply Current Per Amplifier
Capacitive Load Stability
*Guaranteed
by CMR test.
Specifications subject to change without notice.
IVR
CMR
PSRR
V
O
I
SY
3.2
775
µA
nF
ELECTRICAL CHARACTERISTICS
(V =
S
15 V, T
A
= 25 C, unless otherwise noted.)
Min
±
12
OP200A/E
Typ
±
13
135
0.4
±
12
±
11
±
12.6
±
12.2
570
0.1
0.15
500
123
145
3.2
123
725
0.1
1.8
±
12
±
11
Max
Min
±
12
110
OP200G
Typ
±
13
130
0.6
±
12.6
±
12.2
570
0.15
500
145
3.2
10
725
5.6
Max
Unit
V
dB
µV/V
V
V
µA
V/µS
kHz
dB
pF
nF
Parameter
Input Voltage Range
1
Common-Mode
Rejection
Power Supply
Rejection Ratio
Output Voltage
Swing
Supply Current
Per Amplifier
Slew Rate
Gain Bandwidth
Product
Channel Separation
2
Symbol
IVR
CMR
PSRR
V
O
Conditions
V
CM
=
±
12 V
V
S
=
±
3 V
to
±
18 V
R
L
= 10 kΩ
R
L
= 2 kΩ
No Load
120
I
SY
SR
GBWP
CS
A
V
= 1
V
O
= 20 V p-p
f
O
= 10 Hz
A
V
= 1
No Oscillations
Input Capacitance
Capacitive Load
Stability
C
IN
10
NOTES
1
Guaranteed by CMR test.
2
Guaranteed but not 100% tested.
Specifications subject to change without notice.
REV. B
–3–
OP200–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(V =
±15
V, –40 C
≤
T
≤
+85 C, unless otherwise noted.)
S
A
Parameter
Input Offset Voltage
Average Input Offset
Voltage Drift
Input Offset Current
Input Bias Current
Large-Signal
Voltage Gain
Input Voltage
Range*
Common-Mode
Rejection
Power Supply
Rejection Ratio
Output Voltage
Swing
Supply Current
Per Amplifier
Capacitive Load
Stability
*Guaranteed
by CMR test.
Symbol
V
OS
TCV
OS
I
OS
I
B
A
VO
Conditions
Min
OP200E
Typ
35
0.2
Max
100
0.5
2.5
5.0
Min
OP200G
Typ
110
0.6
0.1
0.5
Max
300
2.0
6.0
10.0
Unit
µV
µV/°C
nA
nA
V/mV
V/mV
V
dB
V
CM
= 0 V
V
CM
= 0 V
V
O
=
±
10 V
R
L
= 10 kΩ
R
L
= 2 kΩ
3000
1500
±
12
V
CM
=
±
12 V
V
S
=
±
3 V
to
±
18 V
R
L
= 10 kΩ
R
L
= 2 kΩ
No Load
A
V
= 1
No Oscillations
±
12
±
11
115
0.08
03
10000
3200
±
12.5
130
0.15
±
12.4
±
12
600
10
10
2000
1000
±
12
105
3.2
±
12
±
11
775
5000
2500
±
12.5
130
0.3
±
12.4
±
12.2
600
10
10
775
10.0
IVR
CMR
PSRR
V
O
µV/V
V
V
µA
nF
nF
I
SY
Specifications subject to change without notice.
–4–
REV. B
OP200
1/2
OP200
V
1
20Vp-p @ 10Hz
100
10k
50k
50
1/2
OP200
V
2
1/2
OP200
1/2
OP200
e
OUT
TO SPECTRUM
ANALYZER
CHANNEL SEPARATION = 20 LOG
V
1
V
2
/1000
e
OUT
(nV/
Hz)
=
2
e
OUT
(nV/
Hz)
101
Figure 2. Channel Separation Test Circuit
Figure 3. Noise Test Schematic
ABSOLUTE MAXIMUM RATINGS
1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
20 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . .
±
30 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage
Output Short-Circuit Duration . . . . . . . . . . . . . . Continuous
Storage Temperature Range
P, S, Z-Package . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . 300°C
Junction Temperature (T
J
) . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP200A . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
OP200E . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
OP200G . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Package Type
8-Lead CERDIP (Z)
8-Lead Plastic DIP (P)
16-Lead SOIC (S)
JA
2
JC
Package
T
A
= 25 C
V
OS
Max
( V)
75
75
200
200
200
CERDIP
8-Lead
OP200AZ
OP200EZ
OP200GP
OP200GS
OP200GS-REEL
Operating
Temperature
Range
MIL
XIND
XIND
XIND
XIND
Plastic
Unit
°C/W
°C/W
°C/W
For military processed devices, please refer to the Standard
Microcircuit Drawing (SMD) available at
www.dscc.dla.mil/programs/milspec/default.asp
148
96
92
16
37
27
SMD Part Number
5962-8859301M2A
5962-8859301MPA
ADI Equivalent
OP200ARCMDA
OP200AZMDA
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
JA
is specified for worst-case mounting conditions, i.e.,
JA
is specified for
device in socket for CERDIP and PDIP packages;
JA
is specified for device
soldered to printed circuit board for SOIC package.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP200 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. B
–5–
Embedded System
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