The P2042A is a versatile spread spectrum frequency
modulator designed specifically for digital flat panel
applications.
The
P2042A
reduces
electromagnetic
Applications
The P2042A is targeted towards digital flat panel
applications for notebook PCs, palm-size PCs, office
automation equipments and LCD monitors.
Block Diagram
VDD
SR0 CP1 CP0 SSON#
Modulation
CLKIN
Frequency
Divider
Feedback
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
VSS
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
November 2006
rev 1.4
Pin Configuration
CLKIN
1
CP0
2
8
P2042A
VDD
7
SR0
P2042A
CP1
3
VSS
4
6
5
ModOUT
SSON#
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin
Name
CLKIN
CP0
CP1
VSS
SSON#
ModOUT
SR0
VDD
Type
I
I
I
P
I
O
I
P
Description
External reference frequency input. Connect to externally generated reference signal.
Digital logic input used to select charge pump current. This pin has an internal pull-up
resistor.
Refer Modulation Selection Table.
Digital logic input used to select charge pump current. This pin has an internal pull-up
resistor.
Refer Modulation Selection Table.
Ground to entire chip. Connect to system ground.
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread
Spectrum function enabled when LOW, disabled when HIGH.
This pin has an internal pull-low resistor.
Spread spectrum clock output.
Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor.
Power supply for the entire chip
Modulation Selection
CP0
0
0
0
0
1
1
1
1
CP1
0
0
1
1
0
0
1
1
SR0
0
1
0
1
0
1
0
1
Spreading Range (±%)
32.5MHz
0.56
1.94
1.36
1.92
1.24
1.91
0.91
1.47
54MHz
1.05
1.68
1.05
1.68
0.81
1.29
0.45
0.71
65MHz
1.00
1.56
1.00
1.56
0.66
1.02
0.34
0.54
81MHz
0.98
1.48
0.92
1.48
0.40
0.74
0.05
0.36
108MHz
0.80
1.22
0.67
1.06
0.27
0.43
0.15
0.21
Modulation Rate
(KHz)
(FIN /40) * 62.49
KHz
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 8
November 2006
rev 1.4
Spread Spectrum Selection
P2042A
The
Modulation Selection Table
defines the possible spread spectrum options. The optimal setting should minimize system
EMI to the fullest without affecting system performance. The spreading is described as a percentage deviation of the center
frequency. (Note: The center frequency is the frequency of the external reference input on CLKIN, pin1).
For example, P2042A is designed for high-resolution, flat panel applications and is able to support an XGA (1024 x 768) flat
panel operating at 65MHz (FIN) clock speed. A spreading selection of CP0=0, CP1=1 and SR0=0 provides a percentage
deviation of ±1.00% from F
IN
. This results in the frequency on ModOUT being swept from 65.65 to 64.35MHz at a modulation
rate of 101.54KHz.
Refer Modulation Selection Table.
The example in the following illustration is a common EMI reduction
method for a notebook LCD panel and has already been implemented by most of the leading OEM and mobile graphic
accelerator manufacturers.
Application Schematic for Mobile LCD Graphics Controllers
+3.3V
65MHz from graphics accelerator
1 CLKIN
2 CP0
3 CP1
4 VSS
VDD
SR0
8
7
0.1µF
ModOUT 6
SSON# 5
Modulated 65MHz signal with
±1.00% deviation and
modulation rate of 101.54KHz.
This signal is connected back to
the spread spectrum input pin
(SSIN) of the graphics
accelerator.
P2042A
Digital control for the SS enable
or disable
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 8
November 2006
rev 1.4
Absolute Maximum Ratings
Symbol
VDD, V
IN
T
STG
T
A
T
s
T
J
T
DV
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22- A114-B)
P2042A
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +4.6
-65 to +125
-40 to +85
260
150
2
Unit
V
°C
°C
°C
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
DC Electrical Characteristics
Symbol
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
I
CC
V
DD
t
ON
Z
OUT
Input low voltage
Input high voltage
Input low current
(pull-up resistor on inputs CP0, CP1 and SR0)
Input high current (pull-down resistor on input SSON#)
Output low voltage (V
DD
= 3.3 V, I
OL
= 20 mA)
Output high voltage (V
DD
= 3.3 V, I
OL
= 20 mA)
Static supply current standby mode
Dynamic supply current (3.3V and 10pF loading)
Operating voltage
Power-up time (first locked cycle after power up)
Clock output impedance
Parameter
Min
VSS - 0.3
2.0
–
–
–
2.5
–
9
3.0
–
–
Typ
–
–
–
–
–
–
0.6
16
3.3
0.18
50
Max
0.8
VDD + 0.3
-35
35
0.4
–
–
22
3.6
–
–
Unit
V
V
µA
µA
V
V
mA
mA
V
mS
Ω
AC Electrical Characteristics
Symbol
f
IN
f
OUT
t
LH
*
t
HL
*
t
JC
t
D
Input frequency
Output frequency
Output rise time (measured at 0.8V to 2.0V)
Output fall time (measured at 2.0V to 0.8V)
Jitter (cycle to cycle)
Output duty cycle
Parameter
Min
30
30
0.7
0.6
-
45
Typ
65
65
0.9
0.8
-
50
Max
110
110
1.1
1.0
360
55
Unit
MHz
MHz
nS
nS
pS
%
*t
LH
and t
HL
are measured into a capacitive load of 15pF
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
4 of 8
November 2006
rev 1.4
Package Information
8-lead SOIC Package
P2042A
E
H
D
A2
A
θ
e
B
A
1
C
L
D
Dimensions
Symbol
Min
A1
A
A2
B
C
D
E
e
H
L
θ
Inches
Max
0.010
0.069
0.059
0.020
0.010
0.004
0.053
0.049
0.012
0.007
Millimeters
Min
Max
0.10
1.35
1.25
0.31
0.18
4.90 BSC
3.91 BSC
1.27 BSC
6.00 BSC
0.41
0°
1.27
8°
0.25
1.75
1.50
0.51
0.25
0.193 BSC
0.154 BSC
0.050 BSC
0.236 BSC
0.016
0°
0.050
8°
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
京公网安备 11010802033920号
EEWORLD
