Ascend Semiconductor Corporation
64Mb SDRAM
ASCEND
ASCEND
Semiconductor
64M SDRAM
64M SDRAM
Data sheet
Data sheet
Tel: (03)5635888 / Fax: (03)5635188/ http://www.ascendsemi.com.tw
Preliminary
1
Ascend Semiconductor Corporation
Ordering Information
64Mb SDRAM
AD 48 4M 16 4 4 V T A – 7 L I
Ascend
Semiconductor
Operating Range
I
: Industrial
-40℃ ~ 85℃
Non
: Commercial
0℃ ~ 70℃
S
: Special
0℃ ~ 85℃
EDO
FPM
DDRSDRAM
DDRSGRAM
SGRAM
SDRAM
:
:
:
:
:
:
40
41
42
43
46
48
Density
16M
: 16 Mega Bits
8M
: 8 Mega Bits
4M
: 4 Mega Bits
2M
: 2 Mega Bits
1M
: 1 Mega Bit
Organization
8
: x8
9
: x9
16
: x16
18
: x18
32
: x32
Refresh
1
: 1K,
8
: 8K
2
: 2K,
6
:16K
4
: 4K
Bank
2
: 2Bank
6
: 16Bank
4
: 4Bank
3
: 32Bank
8
: 8Bank
Power
Non : Standard
L
: Low power
Min Cycle Time ( Max Freq.)
-55
: 5.5ns ( 183MHz )
-6
: 6ns
( 167MHz )
-7
: 7ns
( 143MHz )
-8
: 8ns
( 125MHz )
-10
: 10ns ( 100MHz )
-15
: 15ns (66MHz,CL1 applicable)
Revision
A :
1st
B :
2nd
C :
3rd
D :4th
Interface
V:
3.3V
R:
2.5V
Package
C:
CSP
B:
uBGA
T:
TSOP
Q:
TQFP
P:
PQFP ( QFP )
Preliminary
2
Ascend Semiconductor Corporation
64Mb( 4Banks ) Synchronous DRAM
AD484M1644VTA ( 4Mx16 )
Description
64Mb SDRAM
The AD484M1644VTA is Synchronous Dynamic Random Access Memory ( SDRAM )
organized as 1,048,756 words x 4 banks x 16 bits. All inputs and outputs are synchronized
with the positive edge of the clock . The 64Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer rates and is designed to operate in 3.3V
low power memory system. It also provides auto refresh with power saving / down mode.
All inputs and outputs voltage levels are compatible with LVTTL
.
Features
•
Fully synchronous to positive clock edge
• Single 3.3V +/- 0.3V power supply
• LVTTL compatible with multiplexed address
• Industrial temperature available
• Programmable Burst Length ( BL ) - 1,2,4,8 or full page
• Programmable CAS Latency ( CL ) -1, 2 or 3
• Data Mask ( DQM ) for Read/Write masking
• Programmable wrap sequential - Sequential ( BL = 1/2/4/8/full page )
- Interleave ( BL = 1/2/4/8 )
• Burst read with single-bit write operation
• All inputs are sampled at the positive rising edge of the system clock.
• Auto refresh and self refresh
• 4,096 refresh cycles / 64ms
Ordering Information
Part number
AD484M1644VTA-55
Max
Freg.
183MHz
Package
54pins,
TSOPII
54pins,
TSOPII
54pins,
TSOPII
54pins,
TSOPII
54pins,
TSOPII
54pins,
TSOPII
54pins,
TSOPII
Operation Range
Commercial Range : 0℃ ~ 70℃
Power
Standard
Note
AD484M1644VTA-6
167MHz
Commercial Range : 0℃ ~ 70℃
Standard
AD484M1644VTA-7
143MHz
Commercial Range : 0℃ ~ 70℃
Standard
AD484M1644VTA-15
66MHz
Commercial Range : 0℃ ~ 70℃
Standard
CL1
AD484M1644VTA-7L
143MHz
Commercial Range : 0℃ ~ 70℃
Low power
AD484M1644VTA-8L
125MHz
Commercial Range : 0℃ ~ 70℃
Low power
AD484M1644VTA-10L
100MHz
Commercial Range : 0℃ ~ 70℃
Low power
* Ascend Semiconductor reserves the right to change products or specification without notice.
Preliminary
3
Ascend Semiconductor Corporation
Ordering Information
Part number
AD484M1644VTA-7I
64Mb SDRAM
Max
Freg.
143MHz
Package
54pins,
TSOPII
54pins,
TSOPII
54pins,
TSOPII
54pins,
TSOPII
54pins,
TSOPII
54pins,
TSOPII
Operation Range
Industrial Range : -40℃ ~ 85℃
Power
Standard
Note
AD484M1644VTA-8I
125MHz
Industrial Range : -40℃ ~ 85℃
Standard
AD484M1644VTA-10I
100MHz
Industrial Range : -40℃ ~ 85℃
Standard
AD484M1644VTA-7LI
143MHz
Industrial Range : -40℃ ~ 85℃
Low power
AD484M1644VTA-8LI
125MHz
Industrial Range : -40℃ ~ 85℃
Low power
AD484M1644VTA-10LI
100MHz
Industrial Range : -40℃ ~ 85℃
Low power
* Ascend Semiconductor reserves the right to change products or specification without notice.
Pin Assignment ( Top View )
V
DD
1
DQ0
2
V
DDQ
3
DQ1
4
DQ2
5
V
SSQ
6
DQ3
7
DQ4
8
V
DDQ
9
DQ5
10
DQ6
11
V
SSQ
12
DQ7
13
V
DD
14
LDQM
15
/WE
16
/CAS
17
/RAS
18
/CS
19
BA0
20
BA1
21
A10/AP
22
A0
23
A1
24
A2
25
A3
26
V
DD
27
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
Preliminary
54pin TSOP-II
(400milx875mil)
(0.8mm Pin pitch)
4
Ascend Semiconductor Corporation
Pin Descriptions ( Simplified )
64Mb SDRAM
Pin
CLK
/CS
CKE
Name
System Clock
Chip select
Clock Enable
Pin Function
Master Clock Input(Active on the Positive rising edge)
Selects chip when active
Activates the CLK when “H” and deactivates when “L”.
CKE should be enabled at least one cycle prior to new
command. Disable input buffers for power down in standby.
Row address (A0 to A11) is determined by A0 to A11 level
at the bank active command cycle CLK rising edge.
CA(CA0 to CA7) is determined by A0 to A7 level at the
read or write command cycle CLK rising edge.
And this column address becomes burst access start
address. A10 defines the pre-charge mode. When A10 = High
at the pre-charge command cycle, all banks are pre-charged.
But when A10 = Low at the pre-charge command cycle,
only the bank that is selected by BA0/BA1 is pre-charged.
Selects which bank is to be active.
Latches Row Addresses on the positive rising edge of the
CLK with /RAS “L”. Enables row access & pre-charge.
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
A0 ~ A11
Address
BA0, BA1
Bank Address
/RAS
Row address strobe
/CAS
Column address strobe
/WE
Write Enable
LDQM/ UDQM
Data input/output Mask
DQM controls I/O buffers.
DQ0 ~ 15
Data input/output
DQ pins have the same function as I/O pins on a conventional
DRAM.
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
Power supply/Ground
Power supply/Ground
No connection
V
DD
and V
SS
are power supply pins for internal circuits.
V
DDQ
and V
SSQ
are power supply pins for the output buffers.
This pin is recommended to be left No Connection on the
device.
Preliminary
5
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