P82B96
Dual bidirectional bus buffer
Rev. 06 — 31 January 2008
Product data sheet
1. General description
The P82B96 is a bipolar IC that creates a non-latching, bidirectional, logic interface
between the normal I
2
C-bus and a range of other bus configurations. It can interface
I
2
C-bus logic signals to similar buses having different voltage and current levels.
For example, it can interface to the 350
µA
SMBus, to 3.3 V logic devices, and to 15 V
levels and/or low-impedance lines to improve noise immunity on longer bus lengths.
It achieves this interface without any restrictions on the normal I
2
C-bus protocols or clock
speed. The IC adds minimal loading to the I
2
C-bus node, and loadings of the new bus or
remote I
2
C-bus nodes are not transmitted or transformed to the local node. Restrictions
on the number of I
2
C-bus devices in a system, or the physical separation between them,
are virtually eliminated. Transmitting SDA and SCL signals via balanced transmission
lines (twisted pairs) or with galvanic isolation (opto-coupling) is simple because separate
directional Tx and Rx signals are provided. The Tx and Rx signals may be directly
connected, without causing latching, to provide an alternative bidirectional signal line with
I
2
C-bus properties.
2. Features
I
Bidirectional data transfer of I
2
C-bus signals
I
Isolates capacitance allowing 400 pF on Sx/Sy side and 4000 pF on Tx/Ty side
I
Tx/Ty outputs have 60 mA sink capability for driving low-impedance or high capacitive
buses
I
400 kHz operation over at least 20 meters of wire (see
AN10148)
I
Supply voltage range of 2 V to 15 V with I
2
C-bus logic levels on Sx/Sy side
independent of supply voltage
I
Splits I
2
C-bus signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals for interface
with opto-electrical isolators and similar devices that need unidirectional input and
output signal paths.
I
Low power supply current
I
ESD protection exceeds 3500 V HBM per JESD22-A114, 250 V DIP package, 400 V
SO package MM per JESD22-A115, and 1000 V CDM per JESD22-C101
I
Latch-up free (bipolar process with no latching structures)
I
Packages offered: DIP8, SO8 and TSSOP8
NXP Semiconductors
P82B96
Dual bidirectional bus buffer
3. Applications
I
Interface between I
2
C-buses operating at different logic levels (for example, 5 V and
3 V or 15 V)
I
Interface between I
2
C-bus and SMBus (350
µA)
standard
I
Simple conversion of I
2
C-bus SDA or SCL signals to multi-drop differential bus
hardware, for example, via compatible PCA82C250
I
Interfaces with opto-couplers to provide opto-isolation between I
2
C-bus nodes up to
400 kHz.
4. Ordering information
Table 1.
Ordering information
Package
Name
P82B96DP
P82B96PN
P82B96TD
P82B96TD/S410
Description
Version
SOT505-1
SOT97-1
SOT96-1
SOT96-1
TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm
DIP8
SO8
SO8
plastic dual in-line package; 8 leads (300 mil)
plastic small outline package; 8 leads;
body width 3.9 mm
plastic small outline package; 8 leads;
body width 3.9 mm
Type number
4.1 Ordering options
Table 2.
P82B96DP
P82B96PN
P82B96TD
P82B96TD/S410
Ordering options
Topside mark
82B96
P82B96PN
P82B96T
P82B96T
Temperature range
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +125
°C
Type number
P82B96_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 31 January 2008
2 of 28
NXP Semiconductors
P82B96
Dual bidirectional bus buffer
5. Block diagram
V
CC
(2 V to 15 V)
8
P82B96
Sx (SDA)
1
3
2
Sy (SCL)
7
5
6
4
GND
002aab976
Tx (TxD, SDA)
Rx (RxD, SDA)
Ty (TxD, SCL)
Ry (RxD, SCL)
Fig 1.
Block diagram of P82B96
6. Pinning information
6.1 Pinning
P82B96TD
P82B96TD/S410
Sx
Rx
Tx
GND
1
2
8
7
V
CC
Sy
Ry
Ty
Sx
Rx
Tx
GND
1
2
3
4
002aab978
8
7
6
5
V
CC
Sy
Ry
Ty
Sx
Rx
Tx
GND
1
2
3
4
002aab979
8
7
V
CC
Sy
Ry
Ty
P82B96PN
3
4
002aab977
6
5
P82B96DP
6
5
Fig 2.
Pin configuration for DIP8
Fig 3.
Pin configuration for SO8
Fig 4.
Pin configuration for
TSSOP8
6.2 Pin description
Table 3.
Symbol
Sx
Rx
Tx
GND
Ty
Ry
Sy
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
Description
I
2
C-bus (SDA or SCL)
receive signal
transmit signal
negative supply
transmit signal
receive signal
I
2
C-bus (SDA or SCL)
positive supply voltage
P82B96_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 31 January 2008
3 of 28
NXP Semiconductors
P82B96
Dual bidirectional bus buffer
7. Functional description
Refer to
Figure 1 “Block diagram of P82B96”.
The P82B96 has two identical buffers allowing buffering of both of the I
2
C-bus (SDA and
SCL) signals. Each buffer is made up of two logic signal paths, a forward path from the
I
2
C-bus interface pin which drives the buffered bus, and a reverse signal path from the
buffered bus input to drive the I
2
C-bus interface. Thus these paths are:
•
sense the voltage state of the I
2
C-bus pin Sx (or Sy) and transmit this state to the pin
Tx (Ty respectively), and
•
sense the state of the pin Rx (Ry) and pull the I
2
C-bus pin LOW whenever Rx (Ry) is
LOW.
The rest of this discussion will address only the ‘x’ side of the buffer; the ‘y’ side is
identical.
The I
2
C-bus pin (Sx) is designed to interface with a normal I
2
C-bus.
The logic threshold voltage levels on the I
2
C-bus are independent of the IC supply V
CC
.
The maximum I
2
C-bus supply voltage is 15 V and the guaranteed static sink current is
3 mA.
The logic level of Rx is determined from the power supply voltage V
CC
of the chip. Logic
LOW is below 42 % of V
CC
, and logic HIGH is above 58 % of V
CC
(with a typical switching
threshold of half V
CC
).
Tx is an open-collector output without ESD protection diodes to V
CC
. It may be connected
via a pull-up resistor to a supply voltage in excess of V
CC
, as long as the 15 V rating is not
exceeded. It has a larger current sinking capability than a normal I
2
C-bus device, being
able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down
capability as well.
A logic LOW is only transmitted to Tx when the voltage at the I
2
C-bus pin (Sx) is below
0.6 V. A logic LOW at Rx will cause the I
2
C-bus (Sx) to be pulled to a logic LOW level in
accordance with I
2
C-bus requirements (maximum 1.5 V in 5 V applications) but not low
enough to be looped back to the Tx output and cause the buffer to latch LOW.
The minimum LOW level this chip can achieve on the I
2
C-bus by a LOW at Rx is typically
0.8 V.
If the supply voltage V
CC
fails, then neither the I
2
C-bus nor the Tx output will be held LOW.
Their open-collector configuration allows them to be pulled up to the rated maximum of
15 V even without V
CC
present. The input configuration on Sx and Rx also present no
loading of external signals even when V
CC
is not present.
The effective input capacitance of any signal pin, measured by its effect on bus rise times,
is less than 7 pF for all bus voltages and supply voltages including V
CC
= 0 V.
Remark:
Two or more Sx or Sy I/Os must not be interconnected. The P82B96 design
does not support this configuration. Bidirectional I
2
C-bus signals do not allow any
direction control pin so, instead, slightly different logic low voltage levels are used at Sx/Sy
to avoid latching of this buffer. A ‘regular I
2
C-bus LOW’ applied at the Rx/Ry of a P82B96
will be propagated to Sx/Sy as a ‘buffered LOW’ with a slightly higher voltage level. If this
P82B96_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 31 January 2008
4 of 28
NXP Semiconductors
P82B96
Dual bidirectional bus buffer
special ‘buffered LOW’ is applied to the Sx/Sy of another P82B96 that second P82B96 will
not recognize it as a ‘regular I
2
C-bus LOW’ and will not propagate it to its Tx/Ty output.
The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special
logic thresholds for their operation, for example PCA9511, PCA9515, or PCA9518. The
Sx/Sy side is only intended for, and compatible with, the normal I
2
C-bus logic voltage
levels of I
2
C-bus master and slave chips, or even Tx/Rx signals of a second P82B96 if
required. The Tx/Rx and Ty/Ry I/O pins use the standard I
2
C-bus logic voltage levels of all
I
2
C-bus parts. There are
no
restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O
pins to other P82B96s, for example in a star or multipoint configuration with the Tx/Rx and
Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to the line card slave
devices. For more details see
Application Note AN255.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages with respect to pin GND.
Symbol
V
CC
V
Sx
V
Tx
V
Rx
I
n
P
tot
T
j
T
stg
T
amb
Parameter
supply voltage
voltage on pin Sx
voltage on pin Tx
voltage on pin Rx
current on any pin
total power dissipation
junction temperature
storage temperature
ambient temperature
operating
operating range
P82B96TD/S410
Conditions
V
CC
to GND
I
2
C-bus SDA or SCL
buffered output
receive input
Min
−0.3
−0.3
−0.3
−0.3
-
-
−40
−55
−40
Max
+18
+18
+18
+18
250
300
+125
+125
+85
Unit
V
V
V
V
mA
mW
°C
°C
°C
P82B96_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 31 January 2008
5 of 28
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