Nonvolatile, I
2
C-Compatible
64-Position, Digital Potentiometer
AD5258
FEATURES
Nonvolatile memory maintains wiper settings
64-position
Compact MSOP-10 (3 mm × 4.9 mm) package
I
2
C®-compatible interface
V
LOGIC
pin provides increased interface flexibility
End-to-end resistance 1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Resistance tolerance stored in EEPROM (0.1% accuracy)
Power-on EEPROM refresh time <1 ms
Software write protect command
Three-state Address Decode Pins AD0 and AD1 allow
9 packages per bus
100-year typical data retention at 55°C
Wide operating temperature
−40°C
to +85°C
3 V to 5 V single supply
V
DD
V
LOGIC
GND
6
I
2
C
SERIAL
INTERFACE
6
DATA
CONTROL
COMMAND
DECODE LOGIC
ADDRESS
DECODE LOGIC
CONTROL LOGIC
RDAC
EEPROM
RDAC
REGISTER
FUNCTIONAL BLOCK DIAGRAMS
RDAC
A
W
B
SCL
SDA
AD0
AD1
AD5258
05029-001
POWER-
ON RESET
Figure 1. Block Diagram
V
LOGIC
V
DD
A
APPLICATIONS
LCD panel V
COM
adjustment
LCD panel brightness and contrast control
Mechanical potentiometer replacement in new designs
Programmable power supplies
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
Fiber to the home systems
Electronics level settings
SCL
SDA
AD0
AD1
I
2
C
SERIAL
INTERFACE
EEPROM
RDAC
REGISTER
AND
LEVEL
SHIFTER
COMMAND
DECODE LOGIC
ADDRESS
DECODE LOGIC
CONTROL
LOGIC
GND
B
W
Figure 2. Block Diagram Showing Level Shifters
GENERAL DESCRIPTION
The AD5258 provides a compact, nonvolatile 3 mm × 4.9 mm
packaged solution for 64-position adjustment applications.
These devices perform the same electronic adjustment function
as mechanical potentiometers
1
or variable resistors, but with
enhanced resolution and solid-state reliability.
The wiper settings are controllable through an I
2
C-compatible
digital interface that is also used to read back the wiper register
and EEPROM content. Resistor tolerance is also stored within
EEPROM providing an end-to-end tolerance accuracy of 0.1%.
There is also a software write protection function that ensures
data cannot be written to the EEPROM register.
1
CONNECTION DIAGRAM
W
1
AD0
2
10
A
B
AD5258
9
SCL
5
6
V
LOGIC
Figure 3. Pinout
A separate V
LOGIC
pin delivers increased interface flexibility. For
users who need multiple parts on one bus, Address Bit AD0 and
Address Bit AD1 allow up to nine devices on the same bus.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
The terms digital potentiometer, VR (variable resistor), and RDAC are used
interchangeably.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2005 Analog Devices, Inc. All rights reserved.
05029-002
8
V
DD
AD1
3
TOP VIEW
SDA
4
(Not to Scale)
7
GND
05029-003
AD5258
TABLE OF CONTENTS
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Test Circuits..................................................................................... 13
Theory of Operation ...................................................................... 14
Programming the Variable Resistor......................................... 14
Programming the Potentiometer Divider ............................... 14
I
2
C Interface..................................................................................... 15
I
2
C Byte Formats ............................................................................. 16
Generic Interface ........................................................................ 16
Write Modes................................................................................ 17
Read Modes................................................................................. 17
Store/Restore Modes .................................................................. 17
Tolerance Readback Modes ...................................................... 18
ESD Protection of Digital Pins and Resistor Terminals........ 19
Power-Up Sequence ................................................................... 19
Layout and Power Supply Bypassing ....................................... 19
Multiple Devices on One Bus ................................................... 19
Evaluation Board ........................................................................ 19
Display Applications ...................................................................... 20
Circuitry ...................................................................................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
3/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD5258
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
DD
= V
LOGIC
= 5 V ± 10%, or 3 V ± 10%; V
A
= V
DD
; V
B
= 0 V; −40°C < T
A
< +85°C, unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS: RHEOSTAT MODE
Resistor Differential Nonlinearity
1 kΩ
10 kΩ/50 kΩ/100 kΩ
Resistor Integral Nonlinearity
1 kΩ
10 kΩ/100 kΩ
50 kΩ
Nominal Resistor Tolerance
1 kΩ
10 kΩ/50 kΩ/100 kΩ
Resistance Temperature Coefficient
Total Wiper Resistance
DC CHARACTERISTICS:
POTENTIOMETER DIVIDER MODE
Differential Nonlinearity
1 kΩ
10 kΩ/50 kΩ/100 kΩ
Integral Nonlinearity
1 kΩ
10 kΩ/50 kΩ/100 kΩ
Full-Scale Error
1 kΩ
10 kΩ
50 kΩ/100 kΩ
Zero-Scale Error
1 kΩ
10 kΩ
50 kΩ/100 kΩ
Voltage Divider Temperature
Coefficient
RESISTOR TERMINALS
Voltage Range
Capacitance A, B
Capacitance W
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Leakage Current
SDA, AD0, AD1
SCL – Logic High
SCL – Logic Low
Input Capacitance
Symbol
R-DNL
Conditions
R
WB
, V
A
= no connect
−1.5
−0.25
R-INL
R
WB
, V
A
= no connect
−5
−0.5
−0.25
T
A
= 25°C, V
DD
= 5.5 V
R
AB
∆R
AB
(∆R
AB
× 10
6
)/(R
AB
× ∆T)
R
WB
0.9
−30
Code = 0x00/0x20
Code = 0x00
200/15
75
1.5
+30
350
kΩ
%
ppm/°C
Ω
±0.5
±0.1
±0.1
+5
+0.5
+0.25
±0.3
±0.1
+1.5
+0.25
LSB
Min
Typ
1
Max
Unit
LSB
DNL
−1
−0.25
INL
−1
−0.25
V
WFSE
Code = 0x3F
−6
−1
−1
V
WZSE
Code = 0x00
0
0
0
(∆V
W
× 10
6
)/(V
W
× ∆T)
Code = 0x00/0x20
3
0.3
0.1
120/15
5
1
0.5
−3
−0.3
−0.1
0
0
0
±0.3
±0.1
+1
+0.25
±0.3
±0.1
+1
+0.25
LSB
LSB
LSB
LSB
ppm/°C
V
A, B, W
C
A, B
C
W
I
CM
V
IH
V
IL
I
IL
GND
f = 1 MHz, measured to GND,
code = 0x20
f = 1 MHz, measured to GND,
code = 0x20
V
A
= V
B
= V
DD
/2
0.7 × V
L
−0.5
V
IN
= 0 V or 5 V
V
IN
= 0 V
V
IN
= 5 V
0.01
−1.4
0.01
5
45
60
10
V
DD
V
pF
pF
nA
V
L
+ 0.5
0.3 × V
L
±1
+1
±1
V
V
µA
−2.5
C
IL
pF
Rev. 0 | Page 3 of 24
AD5258
Parameter
POWER SUPPLIES
Power Supply Range
Positive Supply Current
Logic Supply
Logic Supply Current
Programming Mode Current (EEPROM)
Power Dissipation
Power Supply Rejection Ratio
DYNAMIC CHARACTERISTICS
Bandwidth −3 dB
Symbol
V
DD
I
DD
V
LOGIC
I
LOGIC
I
LOGIC(PROG)
P
DISS
PSRR
BW
Conditions
Min
2.7
0.5
2.7
V
IH
= 5 V or V
IL
= 0 V
V
IH
= 5 V or V
IL
= 0 V
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V
V
DD
= +5 V ± 10%, Code = 0x20
Code = 0x20
R
AB
= 1 kΩ
R
AB
= 10 kΩ
R
AB
= 50 kΩ
R
AB
= 100 kΩ
R
AB
= 10 kΩ, V
A
= 1 V rms, V
B
= 0,
f = 1 kHz
R
AB
= 10 kΩ, V
AB
= 5 V,
±1 LSB error band
R
WB
= 5 kΩ, f = 1 kHz
3.5
35
20
±0.01
Typ
1
Max
5.5
2
5.5
6
40
±0.06
Unit
V
µA
V
µA
mA
µW
%/%
Total Harmonic Distortion
V
W
Settling Time
Resistor Noise Voltage Density
1
THD
W
t
S
e
N_WB
18000
1000
190
100
0.1
500
9
kHz
kHz
kHz
kHz
%
ns
nV/√Hz
Typical values represent average readings at 25°C and V
DD
= 5 V.
Rev. 0 | Page 4 of 24
AD5258
TIMING CHARACTERISTICS
V
DD
= V
LOGIC
= 5 V ± 10%, or 3 V ± 10%; V
A
= V
DD
; V
B
= 0 V; −40°C < T
A
< +85°C, unless otherwise noted.
Table 2.
Parameter
I
2
C INTERFACE TIMING CHARACTERISTICS
SCL Clock Frequency
t
BUF
Bus Free Time between STOP and START
t
HD;STA
Hold Time (Repeated START)
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU;STA
Setup Time for Repeated START
Condition
t
HD;DAT
Data Hold Time
t
SU;DAT
Data Setup Time
t
F
Fall Time of Both SDA and SCL Signals
t
R
Rise Time of Both SDA and SCL Signals
t
SU;STO
Setup Time for STOP Condition
EEPROM Data Storing Time
EEPROM Data Restoring Time at Power On
1
Symbol
f
SCL
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
EEMEM_STORE
t
EEMEM_RESTORE1
Conditions
Min
0
1.3
0.6
1.3
0.6
0.6
0
100
0.9
300
300
0.6
V
DD
rise time dependant. Measure
without decoupling capacitors at V
DD
and
GND.
V
DD
= 5 V.
26
300
Typ
Max
400
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
ms
µs
After this period, the first clock pulse is
generated.
EEPROM Data Restoring Time upon Restore
Command
1
EEPROM Data Rewritable Time
2
FLASH/EE MEMORY RELIABILITY
Endurance
3
Data Retention
4
1
2
t
EEMEM_RESTORE2
t
EEMEM_REWRITE
300
540
100
700
100
µs
µs
kCycles
Years
During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
Delay time after power-on PRESET prior to writing new EEPROM data.
3
Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
4
Retention lifetime equivalent at junction temperature (T
J
) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV derates
with junction temperature.
SCL
t
8
t
9
t
6
t
2
t
3
t
8
t
9
t
4
t
5
t
7
t
10
P
S
P
Figure 4. I
2
C Interface Timing Diagram
Rev. 0 | Page 5 of 24
05029-004
SDA
t
1
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