Typical values represent average readings at 25°C and V
DD
= 5 V.
Rev. 0 | Page 4 of 24
AD5258
TIMING CHARACTERISTICS
V
DD
= V
LOGIC
= 5 V ± 10%, or 3 V ± 10%; V
A
= V
DD
; V
B
= 0 V; −40°C < T
A
< +85°C, unless otherwise noted.
Table 2.
Parameter
I
2
C INTERFACE TIMING CHARACTERISTICS
SCL Clock Frequency
t
BUF
Bus Free Time between STOP and START
t
HD;STA
Hold Time (Repeated START)
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU;STA
Setup Time for Repeated START
Condition
t
HD;DAT
Data Hold Time
t
SU;DAT
Data Setup Time
t
F
Fall Time of Both SDA and SCL Signals
t
R
Rise Time of Both SDA and SCL Signals
t
SU;STO
Setup Time for STOP Condition
EEPROM Data Storing Time
EEPROM Data Restoring Time at Power On
1
Symbol
f
SCL
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
EEMEM_STORE
t
EEMEM_RESTORE1
Conditions
Min
0
1.3
0.6
1.3
0.6
0.6
0
100
0.9
300
300
0.6
V
DD
rise time dependant. Measure
without decoupling capacitors at V
DD
and
GND.
V
DD
= 5 V.
26
300
Typ
Max
400
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
ms
µs
After this period, the first clock pulse is
generated.
EEPROM Data Restoring Time upon Restore
Command
1
EEPROM Data Rewritable Time
2
FLASH/EE MEMORY RELIABILITY
Endurance
3
Data Retention
4
1
2
t
EEMEM_RESTORE2
t
EEMEM_REWRITE
300
540
100
700
100
µs
µs
kCycles
Years
During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
Delay time after power-on PRESET prior to writing new EEPROM data.
3
Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
4
Retention lifetime equivalent at junction temperature (T
J
) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV derates
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