Multiple Output Timing-Safe™ Peak EMI reduction IC
General Features
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the REF pin. The PLL feedback is on-chip and is obtained
from the CLKOUT pad.
The PCS5P23Z09D has two banks of four outputs each,
which can be controlled by the Select inputs as shown in
the Select Input Decoding Table. The select input also
allows the input clock to be directly applied to the outputs
for chip and system testing purposes.
Multiple PCS5P23Z05D/09D devices can accept the same
input clock and distribute it. In this case the skew between
the outputs of the two devices is guaranteed to be less than
700pS.
All outputs have less than 200pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than ±350pS, and the output to output skew is
guaranteed to be less than 250pS.
Refer
“
Spread Spectrum Control and Input-Output Skew
Table”
for
deviations
and
Input-Output
skew
for
PCS5P23Z05D and PCS5P23Z09D devices.
The PCS5P23Z05D/09D is available in two different
packages, as shown in the ordering information table.
Input frequency range: 100MHz to 150MHz
Clock distribution with Timing-Safe™ Peak EMI
Reduction
Zero input - output propagation delay
Multiple low-skew outputs
Output-output skew less than 250pS
Device-device skew less than 700pS
One input drives 9 outputs, grouped as
4 + 4 + 1(PCS5P23Z09D)
One input drives 5 outputs (PCS5P23Z05D)
Less than 200 pS cycle-to-cycle jitter is compatible
with Pentium based systems
Available in 16pin 150-mil SOIC, 4.4 mm TSSOP
(PCS5P23Z09D), and in 8pin 150-mil SOIC,
4.4mm TSSOP package (PCS5P23Z05D)
®
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3.3V operation
Advanced CMOS technology
The First True Drop-in Solution
Functional Description
PCS5P23Z05D/09D is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed Timing-Safe™ clocks
with Peak EMI reduction. PCS5P23Z09D accepts one
reference input and drives out nine low-skew clocks. It is
available in a 16-pin package. The PCS5P23Z05D is the
eight-pin version of the PCS5P23Z09D. It accepts one
reference input and drives out five low-skew clocks.
All parts have on-chip PLLs that lock to an input clock on
Block Diagram
PLL
REF
PLL
CLKOUT
CLK1
CLKA3
CLK2
CLK3
CLKA4
S2
CLK4
S1
Select Input
Decoding
CLKB1
CLKB2
CLKB3
REF
MUX
CLKOUT
CLKA1
CLKA2
PCS5P23Z05D
PCS5P23Z09D
CLKB4
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
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Tel: 408-879-9077
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Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
May 2007
rev 0.2
Select Input Decoding for PCS5P23Z09D
S2
0
0
1
1
PCS5P23Z05D
PCS5P23Z09D
S1
0
1
0
1
Clock A1 - A4
Three-state
Driven
Driven
Driven
Clock B1 - B4
Three-state
Three-state
Driven
Driven
CLKOUT
1
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL
Shut-Down
N
N
Y
N
Notes:1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and
the output.
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input-output delay.
For applications requiring zero input-output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero-input-output
delay.
Multiple Output Timing-Safe™ Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
2 of 14
May 2007
rev 0.2
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the
edge rates also get faster. Analysis shows that a square
wave is composed of fundamental frequency and
harmonics. The fundamental frequency and harmonics
generate the energy peaks that become the source of
EMI. Regulatory agencies test electronic equipment by
measuring the amount of peak energy radiated from the
equipment. In fact, the peak level allowed decreases as
the frequency increases. The standard methods of
PCS5P23Z05D
PCS5P23Z09D
reducing EMI are to use shielding, filtering, multi-layer
PCBs etc. These methods are expensive. Spread
spectrum clocking reduces the peak energy by reducing
the Q factor of the clock. This is done by slowly
modulating the clock frequency. The PCS5P23Z05D/09D
uses the center modulation spread spectrum technique in
which the modulated output frequency varies above and
below
the
reference
frequency
with
a
specified
modulation rate. With center modulation, the average
frequency is same as the unmodulated frequency and
there is no performance degradation
Timing-Safe™ technology
Timing-Safe™ technology is the ability to modulate a
clock source with Spread Spectrum technology and
maintain synchronization with any associated data path.
Pin Configuration
REF
CLK1
CLK2
GND
1
2
8
7
CLKOUT
CLK4
V
DD
CLK3
PCS5P23Z05D
3
4
6
5
REF
1
CLKA1
CLKA2
V
DD
GND
2
3
4
5
16
CLKOUT
15
CLKA4
14
CLKA3
PCS5P23Z09D
13
V
DD
12
GND
11
CLKB4
10
CLKB3
9
CLKB1
6
CLKB2
7
S2
8
S1
Multiple Output Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 14
May 2007
rev0.2
Pin Description for PCS5P23Z05D
Pin #
1
2
3
4
5
6
7
8
PCS5P23Z05D
PCS5P23Z09D
Pin Name
REF
CLK1
GND
CLK3
1
V
DD
CLK4
1
CLKOUT
1,2
1
Description
Input reference frequency, 5V-tolerant input
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3V supply
Buffered clock output
Buffered clock output, internal feedback on this pin
CLK2
1
Notes: 1. Weak pull-down on these outputs.
2. This output is driven and has an internal feedback for the PLL.
3. Buffered clock outputs are Timing-Safe™
Pin Description for PCS5P23Z09D
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
REF
CLKA1
1
CLKA2
1
V
DD
GND
CLKB1
1
CLKB2
1
S2
2
S1
2
CLKB3
1
CLKB4
1
GND
V
DD
CLKA3
1
CLKA4
1
CLKOUT
1,3
Buffered clock output, bank A
Buffered clock output, bank A
3.3V supply
Ground
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, bank B
Buffered clock output, bank B
Ground
3.3V supply
Buffered clock output, bank A
Buffered clock output, bank A
Description
Input reference frequency, 5V tolerant input
Buffered output, internal feedback on this pin
Notes: 1. Weak pull-down on these outputs.
2. Weak pull-up on these inputs.
3. This output is driven and has an internal feedback for the PLL.
4. Buffered clock outputs are Timing-Safe™
Multiple Output Timing-Safe™ Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
4 of 14
May 2007
rev0.2
Spread Spectrum Control and Input-Output Skew Table
(Note: The values given in the table are for an input frequency of 140MHz)
PCS5P23Z05D
PCS5P23Z09D
Device
PCS5P23Z05D
PCS5P23Z09D
Deviation
±0.125 %
±0.125 %
Input-Output Skew(±T
SKEW
)
0.075
0.075
Note: T
SKEW
is measured in units of the Clock Period
Absolute Maximum Ratings
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
Storage Temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
Min
-0.5
-0.5
-0.5
-65
Max
7
V
DD
+ 0.5
7
+150
260
150
2
Unit
V
V
V
°C
°C
°C
KV
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can
affect device reliability.
Operating Conditions for PCS5P23Z05D and PCS5P23Z09D
Parameter
V
DD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
Description
Min
3.0
0
Max
3.6
70
10
7
Unit
V
°C
pF
pF
Multiple Output Timing-Safe™ Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
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