a
FEATURES
High Integration: 32-Channel DAC in 12 12 mm
2
LFBGA
Adjustable Voltage Output Range
Guaranteed Monotonic
Readback Capability
DSP-/Microcontroller-Compatible Serial Interface
Output Impedance
0.5 (AD5532-1, AD5532-2)
500 (AD5532-3)
1 k (AD5532-5)
Output Voltage Span
10 V (AD5532-1, AD5532-3, AD5532-5)
20 V (AD5532-2)
Infinite Sample-and-Hold Capability to 0.018% Accuracy
Temperature Range –40 C to +85 C
APPLICATIONS
Level Setting
Instrumentation
Automatic Test Equipment
Industrial Control Systems
Data Acquisition
Low Cost I/O
32-Channel, 14-Bit
Voltage-Output DAC
AD5532*
GENERAL DESCRIPTION
The AD5532 is a 32-channel voltage-output 14-bit DAC with
an additional infinite sample-and-hold mode. The selected DAC
register is written to via the 3-wire serial interface and V
OUT
for this DAC is then updated to reflect the new contents of the
DAC register. DAC selection is accomplished via address bits
A0–A4. The output voltage range is determined by the offset
voltage at the OFFS_IN pin and the gain of the output amplifier.
It is restricted to a range from V
SS
+ 2 V to V
DD
– 2 V because
of the headroom of the output amplifier.
The device is operated with AV
CC
= 5 V
±
5%, DV
CC
= 2.7 V
to 5.25 V, V
SS
= –4.75 V to –16.5 V and V
DD
= 8 V to 16.5 V
and requires a stable +3 V reference on REF_IN as well as an
offset voltage on OFFS_IN.
PRODUCT HIGHLIGHTS
1. 32-channel, 14-bit DAC in one package, guaranteed
monotonic.
2. The AD5532 is available in a 74-lead LFBGA package with
a body size of 12 mm
×
12 mm.
3. Droopless/Infinite Sample-and-Hold Mode.
FUNCTIONAL BLOCK DIAGRAM
DV
CC
AV
CC
REF IN
REF OUT
OFFS IN
V
DD
V
SS
AD5532
V
OUT
0
V
IN
TRACK
/
RESET
BUSY
DAC GND
AGND
DGND
MUX
MODE
ADC
14-BIT BUS
DAC
V
OUT
31
DAC
OFFS OUT
DAC
SER /
PAR
INTERFACE
CONTROL
LOGIC
SYNC
/
CS
ADDRESS INPUT REGISTER
WR
SCLK D
IN
D
OUT
A4 –A0
CAL
OFFSET SEL
*Protected
by U.S. Patent No. 5,969,657; other patents pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
(V
8 V to 16.5
V; AV
4.75 V to 5.25 V; DV = 2.7
AD5532–SPECIFICATIONS
Output=Range from V, V+ 2=V–4.75 V–to2–16.5 outputs=unloaded. All specifications TV to
5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V;
V
to V
V. All
DD
SS
CC
CC
SS
DD
MIN
to T
MAX
unless otherwise noted.)
Parameter
1
DAC DC PERFORMANCE
Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset
Gain
Full-Scale Error
VOLTAGE REFERENCE
REF_IN
Nominal Input Voltage
Input Voltage Range
3
Input Current
REF_OUT
Output Voltage
Output Impedance
3
Reference Temperature Coefficient
3
ANALOG OUTPUTS (V
OUT
0–31)
Output Temperature Coefficient
3, 4
DC Output Impedance
3
AD5532-1
AD5532-3
AD5532-5
Output Range
Resistive Load
3, 5
Capacitive Load
3, 5
AD5532-1
AD5532-3
AD5532-5
Short-Circuit Current
3
DC Power-Supply Rejection Ratio
3
DC Crosstalk
3
ANALOG OUTPUT (OFFS_OUT)
Output Temperature Coefficient
3, 4
DC Output Impedance
3
Output Range
Output Current
Capacitive Load
DIGITAL INPUTS
3
Input Current
Input Low Voltage
Input High Voltage
Input Hysteresis (SCLK and
CS
Only)
Input Capacitance
DIGITAL OUTPUTS (BUSY, D
OUT
)
3
Output Low Voltage, DV
CC
= 5 V
Output High Voltage, DV
CC
= 5 V
Output Low Voltage, DV
CC
= 3 V
Output High Voltage, DV
CC
= 3 V
High Impedance Leakage Current
High Impedance Output Capacitance
A Version
2
AD5532-1/-3/-5
AD5532-2 Only
14
±
0.39
±
1
90/170/250
3.52
±
2
14
±
0.39
±
1
180/350/500
7
±
2
Unit
Bits
% of FSR max
LSB max
mV min/typ/max
typ
% of FSR max
Conditions/
Comments
±
0.15% typ
±
0.5% typ, Monotonic
See Figure 6
3.0
2.85/3.15
1
3
280
60
20
0.5
500
1
V
SS
+ 2/V
DD
– 2
5
500
15
40
10
–70
–70
250
20
1.3
50 to REF_IN–12
10
100
±
10
0.8
0.4
2.4
2.0
200
10
0.4
4.0
0.4
2.4
±
1
15
3.0
2.85/3.15
1
3
280
60
20
0.5
V
V min/max
µA
max
V typ
kΩ typ
ppm/°C typ
ppm/°C typ
Ω
typ
Ω
typ
kΩ typ
V min/max
kΩ min
pF max
nF max
nF max
mA typ
dB typ
dB typ
µV
max
ppm/°C typ
kΩ typ
mV typ
µA
max
pF max
µA
max
V max
V max
V min
V min
mV typ
pF max
V max
V min
V max
V min
µA
max
pF typ
< 1 nA typ
V
SS
+ 2 /V
DD
– 2
5
500
100
µA
Output Load
10
–70
–70
250
20
1.3
50 to REF_IN–12
10
100
±
10
0.8
0.4
2.4
2.0
200
10
0.4
4.0
0.4
2.4
±
1
15
V
DD
= +15 V
±
5%
V
SS
= –15 V
±
5%
Source Current
±
5
µA
typ
DV
CC
= 5 V
±
DV
CC
= 3 V
±
DV
CC
= 5 V
±
DV
CC
= 3 V
±
5%
10%
5%
10%
Sinking 200
µA
Sourcing 200
µA
Sinking 200
µA
Sourcing 200
µA
D
OUT
Only
D
OUT
Only
–2–
REV. 0
AD5532
Parameter
1
POWER REQUIREMENTS
Power-Supply Voltages
V
DD
V
SS
AV
CC
DV
CC
Power-Supply Currents
6
I
DD
I
SS
AICC
DICC
Power Dissipation
6
AC CHARACTERISTICS
3
Output Voltage Settling Time
OFFS_IN Settling Time
Digital-to-Analog Glitch Impulse
Digital Crosstalk
Analog Crosstalk
Digital Feedthrough
Output Noise Spectral Density @ 1 kHz
A Version
2
AD5532-1/-3/-5
AD5532-2 Only
Unit
Conditions/
Comments
8/16.5
–4.75/–16.5
4.75/5.25
2.7/5.25
15
15
33
1.5
280
22
10
1
5
1
0.2
400
8/16.5
–4.75/–16.5
4.75/5.25
2.7/5.25
15
15
33
1.5
280
30
20
1
5
1
0.2
400
5
6
V min/max
V min/max
V min/max
V min/max
mA max
mA max
mA max
mA max
mW typ
µs
max
µs
max
nV-s typ
nV-s typ
nV-s typ
nV-s typ
nV/(√Hz) typ
10 mA typ.
All Channels Full-Scale
10 mA typ.
All Channels Full-Scale
26 mA typ
1 mA typ
V
DD
= 10 V, V
SS
= –5 V
500 pF, 5 kΩ Load
Full-Scale Change
500 pF, 5 kΩ Load;
0 V–3 V Step
1 LSB Change Around
Major Carry
NOTES
1
See Terminology.
2
A Version: Industrial temperature range –40°C to +85°C; typical at +25°C.
3
Guaranteed by design and characterization, not production tested.
4
AD780 as reference for the AD5532.
Ensure that you do not exceed T
J
(max). See Maximum Ratings.
Output unloaded.
Specifications subject to change without noti
ce.
SHA MODE
Parameter
1
ANALOG CHANNEL
V
IN
to V
OUT
Nonlinearity
3
Offset Error
Gain
ANALOG INPUT (V
IN
)
Input Voltage Range
Input Lower Deadband
Input Upper Deadband
Input Current
Input Capacitance
4
ANALOG INPUT (OFFS_IN)
Input Current
AC CHARACTERISTICS
Output Settling Time
4
Acquisition Time
AC Crosstalk
4
NOTES
1
S
ee Terminology.
2
3
A Version
2
AD5532-1/-3/-5
AD5532-2 Only
±
0.018
±
50
3.46/3.52/3.6
0 to 3
70
40
1
20
1
3
16
5
±
0.018
±
100
6.88/7/7.12
0 to 3
70
40
1
20
1
3
16
5
Unit
% max
mV max
min/typ/max
V
mV max
mV max
µA
max
pF typ
µA
max
µs
max
µs
max
nV-s typ
Conditions/
Comments
±
0.006% typ after Offset and
Gain Adjustment
±
10 mV typ. See Figure 7
See Figure 7
Nominal Input Range
50 mV typ. Referred to V
IN
.
See Figure 7
12 mV typ. Referred to V
IN
.
See Figure 7
100 nA typ.
V
IN
Acquired on 1 Channel
100 nA typ
Output Unloaded
A version: Industrial temperature range –40°C to +85°C; typical at +25°C.
Input range 100 mV to 2.96 V.
4
Guaranteed by design and characterization, not production tested.
Specifications subject to change
without notice.
REV. 0
–3–
AD5532
TIMING CHARACTERISTICS
PARALLEL INTERFACE
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
1, 2
Limit at T
MIN
, T
MAX
(A Version)
0
0
50
50
20
0
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
CS
to
WR
Setup Time
CS
to
WR
Hold Time
CS
Pulsewidth Low
WR
Pulsewidth Low
A4–A0, CAL, OFFS_SEL to
WR
Setup Time
A4–A0, CAL, OFFS_SEL to
WR
Hold Time
NOTES
1
See Interface Timing Diagram.
2
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
SERIAL INTERFACE
Parameter
f
CLKIN3
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8 4
t
9 4
t
10
t
11
1, 2
Limit at T
MIN
, T
MAX
(A Version)
14
28
28
10
50
10
5
5
20
60
400
400
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
Conditions/Comments
SCLK Frequency
SCLK High Pulsewidth
SCLK Low Pulsewidth
SYNC
Falling Edge to SCLK Falling Edge Setup Time
SYNC
Low Time
D
IN
Setup Time
D
IN
Hold Time
SYNC
Falling Edge to SCLK Rising Edge Setup Time
SCLK Rising Edge to D
OUT
Valid
SCLK Falling Edge to D
OUT
High Impedance
10th SCLK Falling Edge to
SYNC
Falling Edge for Readback
24th SCLK Falling Edge to
SYNC
Falling Edge for DAC Mode Write
NOTES
1
See Serial Interface Timing Diagrams.
2
Guaranteed by design and characterization, not production tested.
3
In SHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns.
4
These numbers are measured with the load circuit of Figure 2.
Specifications subject to change without notice.
PARALLEL INTERFACE TIMING DIAGRAMS
CS
TO
OUTPUT
PIN
200 A
I
OL
WR
1.6V
C
L
50pF
200 A
I
OH
A4–A0, CAL,
OFFS SEL
Figure 1. Parallel Write (SHA Mode Only)
Figure 2. Load Circuit for D
OUT
Timing Specifications
–4–
REV. 0
AD5532
SERIAL INTERFACE TIMING DIAGRAMS
t
1
SCLK
1
t
3
2
t
2
3
4
5
6
7
8
9
10
SYNC
t
4
t
5
t
6
D
IN
MSB
LSB
Figure 3. 10-Bit Write (SHA Mode and Both Readback Modes)
t
1
SCLK
1
t
3
2
t
2
3
4
5
21
22
23
24
1
SYNC
t
4
t
5
t
6
t
11
D
IN
MSB
LSB
Figure 4. 24-Bit Write (DAC Mode)
t
1
SCLK
10
t
7
1
2
t
2
3
4
5
6
7
8
9
10
11
12
13
14
SYNC
t
10
D
OUT
MSB
t
4
t
8
t
9
LSB
Figure 5. 14-Bit Read (Both Readback Modes)
REV. 0
–5–
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