ICS8537-01
H
EX
, L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-3.3V/2.5V LVPECL C
LOCK
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8537-01 is a Hex low skew, high performance 1-to-2
Differential-to-3.3V/2.5 LVPECL Clock Buffer. The ICS8537-
01 has six selectable clock inputs. The CLKx, nCLKx pairs
can accept most differential input levels and translate them to
3.3V or 2.5V LVPECL output levels.Guaranteed output and
part-to-part skew specifications make the ICS8537-01 ideal
for those applications demanding well defined performance
and repeatability.
F
EATURES
•
Twelve LVPECL outputs
•
Selectable differential CLKx, nCLKx inputs
•
CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•
Maximum output frequency: 700MHz
•
Translates any differential input signal (LVHSTL, SSTL,
DCM) to LVPECL levels without external bias networks
•
Translates any single-ended input signal to LVPECL
with resistor bias on nCLKx input
•
Output skew: 130ps (maximum)
•
Bank skew: 20ps (maximum)
•
Part-to-part skew: 350ps (maximum)
•
Propagation delay: 1.5ns (maximum)
•
3.3V or 2.5V operating supply
•
0°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free
(RoHS 6) packages
B
LOCK
D
IAGRAM
CLK0
nCLK0
Q0A
nQ0A
Q0B
nQ0B
Q1A
nQ1A
Q1B
nQ1B
Q2A
nQ2A
Q2B
nQ2B
Q3A
nQ3A
Q3B
nQ3B
Q4A
nQ4A
Q4B
nQ4B
Q5A
nQ5A
Q5B
nQ5B
P
IN
A
SSIGNMENT
nQ2A
Q2A
V
CCO
Q2B
nQ2B
V
CC
V
EE
nQ3A
Q3A
V
CCO
Q3B
nQ3B
CLK1
nCLK1
CLK2
nCLK2
CLK3
nCLK3
nQ4A
Q4A
V
CCO
Q4B
nQ4B
V
CC
V
EE
nQ5B
Q5B
V
CCO
Q5A
nQ5A
48
47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
ICS8537-01
nQ1B
Q1B
V
CCO
Q1A
nQ1A
V
CC
V
EE
nQ0B
Q0B
V
CCO
Q0A
nQ0A
nCLK0
CLK0
nCLK1
CLK1
nCLK2
CLK2
nCLK3
CLK3
nCLK4
CLK4
nCLK5
CLK5
CLK4
nCLK4
CLK5
nCLK5
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8537AY-01
www.idt.com
1
REV. B NOVEMBER 22, 2010
ICS8537-01
H
EX
, L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-3.3V/2.5V LVPECL C
LOCK
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 10, 27, 34,
39, 46
4, 5
6, 31, 42
7, 30, 43
8, 9
11, 12
13
14
15
16
17
18
19
20
21
22
23
24
25, 26
28, 29
32, 33
35, 36
37, 38
40, 41
44, 45
47, 48
Name
nQ4A, Q4A
V
CCO
Q4B, nQ4B
V
CC
V
EE
nQ5B, Q5B
Q5A, nQ5A
CLK5
nCLK5
CLK4
nCLK4
CLK3
nCLK3
CLK2
nCLK2
CLK1
nCLK1
CLK0
nCLK0
nQ0A, Q0A
Q0B, nQ0B
nQ1A, Q1A
Q1B, nQ1B
nQ2A, Q2A
Q2B, nQ2B
nQ3A, Q3A
Q3B, nQ3B
Output
Power
Output
Power
Power
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Type
Description
Differential output pair. LVPECL interface levels.
Output supply pins.
Differential output pair. LVPECL interface levels.
Core supply pins.
Negative supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Inver ting differential clock input.
Non-inver ting differential clock input.
Non-inver ting differential clock input.
Inver ting differential clock input.
Non-inver ting differential clock input.
Inver ting differential clock input.
Non-inver ting differential clock input.
Inver ting differential clock input.
Non-inver ting differential clock input.
Inver ting differential clock input.
Non-inver ting differential clock input.
Inver ting differential clock input.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8537AY
-01
www.idt.com
2
REV. B NOVEMBER 22, 2010
ICS8537-01
H
EX
, L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-3.3V/2.5V LVPECL C
LOCK
B
UFFER
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLKx
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLKx
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Outputs
Q0A:Q5A,
nQ0A:nQ5A,
Q0B:Q5B
nQ5B:nQ5B
LOW
HIGH
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single ended levels".
8537AY-01
www.idt.com
3
REV. B NOVEMBER 22, 2010
ICS8537-01
H
EX
, L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-3.3V/2.5V LVPECL C
LOCK
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5 V
-0.5V to V
CCO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 2.375V
TO
3.465V, T
A
= 0°C
TO
85°C
Symbol
V
CC
V
CCO
I
EE
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
3.3
3.3
Maximum
3.465
3.465
130
Units
V
V
mA
T
ABLE
4B. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 2.375V
TO
3.465V, T
A
= 0°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
CLKx
nCLKx
Input Low Current
CLKx
nCLKx
Test Conditions
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
0.15
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Voltage
Common Mode Voltage; NOTE 1, 2
V
EE
+ 0.5
V
CMR
NOTE 1: For single ended appliations, the maximum input voltage for CLK, nCLK is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 2.375V
TO
3.465V, T
A
= 0°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
8537AY
-01
www.idt.com
4
REV. B NOVEMBER 22, 2010
ICS8537-01
H
EX
, L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-3.3V/2.5V LVPECL C
LOCK
B
UFFER
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCO
= 2.375V
TO
3.465V, T
A
= 0°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
Bank Skew; NOTE 3, 5
Par t-to-Par t Skew; NOTE 4, 5
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
IJ 300MHz
200
47
IJ 700MHz
1.1
1.3
Test Conditions
Minimum
Typical
Maximum
700
1.5
130
20
350
600
53
55
Units
MHz
ns
ps
ps
ps
ps
%
%
t
sk(o)
t
sk(b)
t
sk(pp)
t
R
/ t
F
odc
ƒ > 300MHz, ƒ
≤
500MHz
45
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured from at the output differential cross points.
NOTE 3: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 4: Defined as between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
8537AY-01
www.idt.com
5
REV. B NOVEMBER 22, 2010
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