• 1 to 10 differential clock distribution (SSTL_18)
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• Auto PD when input signal is at a certain logic state
Switching Characteristics:
• Period jitter: 40ps (DDR2-400/533)
30ps (DDR2-667/800)
• Half-period jitter: 60ps (DDR2-400/533)
50ps (DDR2-667/800)
• OUTPUT - OUTPUT skew: 40ps (DDR2-400/533)
30ps (DDR2-667/800)
• CYCLE - CYCLE jitter 40ps
Pin Configuration
1
A
B
C
D
E
F
G
H
J
K
2
3
4
5
6
52-Ball BGA
Top View
A
B
C
D
E
F
G
H
J
K
1
CLKT1
CLKC1
CLKC2
CLKT2
CLK_INT
CLK_INC
AGND
AVDD
CLKT3
CLKC3
2
CLKT0
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
GND
GND
CLKC4
CLKC1
CLKT1
CLKT0
Block Diagram
LD or OE
OE
OS
AV
DD
(1)
3
CLKC0
GND
NB
VDDQ
NB
NB
VDDQ
NB
GND
CLKT4
CLKC5
CLKC0
4
CLKC5
GND
NB
VDDQ
NB
NB
VDDQ
NB
GND
CLKT9
CLKT6
CLKC6
CLKT5
5
CLKT5
GND
GND
OS
VDDQ
OE
VDDQ
GND
GND
CLKC9
6
CLKT6
CLKC6
CLKC7
CLKT7
FB_INT
FB_INC
FB_OUTC
FB_OUTT
CLKT8
CLKC8
V
DDQ
POWER
DOWN
AND
LD, OS, or OE
TEST
MODE
PLL BYPASS
LOGIC
LD
CLKT0
CLKC0
39
32
35
34
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
40
38
37
36
33
31
V
DDQ
V
DDQ
CLKC2
CLKT2
CLK_INT
CLK_INC
V
DDQ
AGND
AV
DD
V
DDQ
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
30
29
28
27
26
25
24
23
22
21
CLKC7
CLKT7
V
DDQ
FB_INT
FB_INC
FBOUTC
FBOUTT
V
DDQ
OE
OS
CLK_INT
CLK_INC
10KΩ - 100KΩ
FBIN_INT
FBIN_INC
PLL
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
V
DDQ
CLKT3
CLKT4
CLKC3
CLKC4
CLKC9
CLKT9
CLKC9
NOTE:
1. The Logic Detect (LD) powers down the device
when a logic LOW is applied to both CLK_INT and
CLK_INC.
FBOUTT
FBOUTC
40-Pin MLF
1177D—11/9/07
ADVANCE INFORMATION
documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
CLKC8
CLKT9
CLKT8
V
DDQ
CLKC8
ICS98ULPA877A
Advance Information
Pin Descriptions
Te r m i n a l
Name
AGND
AV
DD
CLK_INT
CLK_INC
FB_INT
FB_INC
FB_OUTT
FB_OUTC
OE
OS
GND
V
DDQ
CLKT[0:9]
CLKC[0:9]
NB
Analog Ground
A n a l o g p ow e r
C l o ck i n p u t w i t h a ( 1 0 K - 1 0 0 K O h m ) p u l l d o w n r e s i s t o r
Complentar y clock input with a (10K-100K Ohm) pulldown resistor
Feedback clock input
Complementary feedback clock input
Feedback clock output
Complementary feedback clock output
Output Enable (Asynchronous)
Output Select (tied to GND or V
DDQ
)
Ground
Logic and output power
Clock outputs
Complementary clock outputs
No ball
Description
Electrical
Characteristics
Ground
1.8 V nominal
Differential input
Differential input
Differential input
Differential input
Differential output
Differential output
LVCMOS input
LVCMOS input
Ground
1.8V nominal
Differential outputs
Differential outputs
The PLL clock buffer,
ICS98ULPA877A,
is designed for a V
DDQ
of 1.8 V, a AV
DD
of 1.8 V and differential data input and
output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF.
ICS98ULPA877A
is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT,
FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT,
FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except
FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output
Select) is a program pin that must be tied to GND or V
DDQ
. When OS is high, OE will function as described above. When
OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC). When AV
DD
is grounded, the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic
detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform
a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic
low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL
will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC)
within the specified stabilization time t
STAB
.
The PLL in
ICS98ULPA877A
clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]).
ICS98ULPA877A
is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
1177D—11/9/07
2
ICS98ULPA877A
Advance Information
ICS98ULPA877A
is available in Commercial Temperature Range (0°C to 70°C) and Industrial Temperature Range (-40°C
to +85°C). See Ordering Information for details
Function Table
Inputs
AVDD
GND
GND
GND
GND
1.8V(nom)
1.8V(nom)
1.8V(nom)
1.8V(nom)
1.8V(nom)
1.8V(nom)
OE
H
H
L
L
L
L
H
H
X
X
OS
X
X
H
L
H
L
X
X
X
X
CLK_INT
L
H
L
H
L
H
L
H
L
H
CLK_INC
H
L
H
L
H
L
H
L
L
H
CLKT
L
H
*L(Z)
*L(Z),
CLKT7
active
*L(Z)
*L(Z),
CLKT7
active
L
H
*L(Z)
CLKC
H
L
*L(Z)
*L(Z),
CLKC7
active
*L(Z)
*L(Z),
CLKC7
active
H
L
*L(Z)
Outputs
PLL
FB_OUTT
L
H
L
H
L
H
FB_OUTC
H
L
H
L
Bypassed/Off
Bypassed/Off
Bypassed/Off
Bypassed/Off
H
L
On
On
L
H
*L(Z)
Reser ved
H
L
*L(Z)
On
On
Off
*L(Z) means the outputs are disabled to a low stated meeting the I
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