The LOGDAC® AD7112 is a monolithic dual multiplying D/A
converter featuring wide dynamic range and excellent DAC-to-
DAC matching. Both DACs can attenuate an analog input sig-
nal over the range 0 dB to 88.5 dB in 0.375 dB steps. It is
available in skinny 0.3" wide 20-pin DIPs and in 20-terminal
surface mount packages.
The degree of attenuation in either channel is determined by the
8-bit word applied to the onboard decode logic. This 8-bit word
is decoded into a 17-bit word which is then loaded into one of
the 17-bit data latches, determined by
DACA/DACB.
The fine
step resolution over the entire dynamic range is due to the use of
these 17-bit DACs.
The AD7112 is easily interfaced to a standard 8-bit MPU bus
via an 8-bit data port and standard microprocessor control lines.
It should be noted that the AD7112 is exactly pin-compatible
with the AD7528, an industry standard dual 8-bit multiplying
DAC. This allows an easy upgrading of existing AD7528 de-
signs which would benefit both from the wider dynamic range
and the finer step resolution offered by the AD7112.
The AD7112 is fabricated in Linear Compatible CMOS
(LC
2
MOS), an advanced, mixed technology process that com-
bines precision bipolar circuits with low power CMOS logic.
*Protected
by U.S. Patent No. 4521764.
LOGDAC is a registered trademark of Analog Devices, Inc.
PRODUCT HIGHLIGHTS
1. DAC-to-DAC Matching: Since both of the AD7112 DACs
are fabricated at the same time on the same chip, precise
matching and tracking between the two DACs is inherent.
2. Small Package: The AD7112 is available in a 20-pin DIP
and a 20-terminal SOIC package.
3. Fast Microprocessor Interface: The AD7112 has bus inter-
face timing compatible with all modern microprocessors.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD7112–SPECIFICATIONS
(V = +5toVT
Output amplifier AD712 except where noted. All specifications T
DD
MIN
5%; OUT A = OUT B = AGND = DGND = 0 V; V
IN
A = V
IN
B = 10 V.
MAX
unless otherwise noted.)
Parameter
ACCURACY
Resolution
Accuracy Relative to
0 dB Attenuation
0.375 dB Steps:
Accuracy
≤ ±
0.17 dB
Monotonic
0.75 dB Steps:
Accuracy
≤ ±
0.35 dB
Monotonic
1.5 dB Steps:
Accuracy
≤ ±
0.7 dB
Monotonic
3.0 dB Steps:
Accuracy
≤ ±
1.4 dB
Monotonic
6.0 dB Steps:
Accuracy
≤ ±
2.7 dB
Monotonic
Gain Error
C Version
T
A
=
T
A
=
+25 C
T
MIN
, T
MAX
0.375
0.375
1
B Version
T
A
=
T
A
=
+25 C
T
MIN
, T
MAX
0.375
0.375
Units
dB
Conditions/Comments
Guaranteed Attenuation
Ranges for Specified Step Sizes.
0 to 36
0 to 54
0 to 48
0 to 72
0 to 36
0 to 54
0 to 42
0 to 66
0 to 30
0 to 48
0 to 42
0 to 72
0 to 48
0 to 85.5
0 to 30
0 to 48
0 to 36
0 to 60
0 to 42
0 to 72
dB min
dB min
dB min
dB min
dB min
dB min
dB min
dB min
dB min
dB min
dB max
0 to 54
0 to 48
Full Range 0 to 78
0 to 66
0 to 54
Full Range Full Range
0 to 72
0 to 60
Full Range Full Range
±
0.1
±
0.15
Full Range Is 0 dB to 88.5 dB.
0 to 60
0 to 48
Full Range Full Range
0 to 60
0 to 60
Full Range Full Range
±
0.15
±
0.2
Measured Using R
FB
A,
R
FB
B. Both DAC Registers
Loaded With All 0s.
Output Leakage Current
OUT A, OUT B
Input Resistance,
V
IN
A, V
IN
B
Input Resistance Match
Feedback Resistance,
R
FB
A, R
FB
B
LOGIC INPUTS
CS, WR,
DAC A/DAC
B,
DB0–DB7
Input Low Voltage, V
INL
Input High Voltage, V
INH
Input Leakage Current
Input Capacitance
2
POWER REQUIREMENTS
V
DD
, Range
3
±
50
9/15
±
1
9.3/15.7
±
400
9/15
±
1
9.3/15.7
±
50
9/15
±
2
9.3/15.7
±
400
9/15
±
2
9.3/15.7
nA max
kΩ min/max Typically 12 kΩ.
% max
kΩ min/max
0.8
2.4
±
1
10
4.75/5.25
2
2
0.8
2.4
±
10
10
4.75/5.25
2
2
0.8
2.4
±
1
10
4.75/5.25
2
2
0.8
2.4
±
10
10
4.75/5.25
2
2
V max
V min
µA
max
pF max
V min/max
mA max
mA max
For Specified Performance.
Logic Inputs = V
IL
or V
IH
Logic Inputs = 0 V or V
DD
NOTES
l
Temperature range as follows: B, C Versions: –40°C to +85°C.
2
Guaranteed by design, not production tested.
3
The part will function with V
DD
= 5 V
±
10% with degraded performance.
Specifications subject to change without notice.
–2–
REV. 0
AD7112
TIMING SPECIFICATIONS
1
(V
Parameter
CS
to
WR
Setup Time
CS
to
WR
Hold Time
DAC Select to
WR
Setup Time
DAC Select to
WR
Hold Time
Data Valid to
WR
Setup Time
Data Valid to
WR
Hold Time
WR
Pulse Width
t
CS
t
CH
t
AS
t
AH
t
DS
t
DH
t
WR
DD
= +5 V
5%; 0UT A = OUT B = AGND = DGND = O V; V
IN
A = V
IN
B = 10 V)
T
A
= –40 C to +85 C
0
0
4
0
55
10
53
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
See Figure 3.
T
A
= +25 C
0
0
4
0
55
10
53
NOTES
1
Timing specifications guaranteed by design not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage
level of 1.6 V.
Specifications subject to change without notice.
AC PERFORMANCE CHARACTERISTICS
Parameter
DC Supply Rejection
∆
Gain/∆ V
DD
Digital-to-Analog Glitch Impulse
Output Capacitance, C
OUT A
, C
OUT B
AC Feedthrough
V
IN
A to OUT A
V
IN
B to OUT B
Channel-to-Channel Isolation
V
IN
A to OUT B
V
IN
B to OUT A
Digital Feedthrough
Output Noise Voltage Density
(30 Hz to 50 kHz)
Total Harmonic Distortion
NOTES
1
Guaranteed by design, not production tested.
Specifications subject to change without notice.
1
(V
DD
= +5 V
5%; 0UT A = OUT B = AGND = DGND = 0 V; V
IN
A =
V
IN
B = 10 V. Output amplifier AD712 except where noted.)
T
A
=
+25 C
0.001
10
50
–94
–94
–87
–87
1
15
–91
T
A
=
–40 C to
+85 C
0.005
10
50
–90
–90
–87
–87
1
15
–91
Units
dB/% max
nV s typ
pF max
dB max
dB max
dB typ
dB typ
nV s typ
nV/√Hz typ
dB typ
Conditions/Comments
∆
V
DD
=
±
5%. Input Code = 00000000
Measured with AD843 as output amplifier for input
code transition 10000000 to 00000000.
V
IN
A, V
IN
B = 6 V rms at 1 kHz. DAC
Registers loaded with all 1s.
V
IN
A = 6 V rms at 10 kHz sine wave,
V
IN
B = 0 V. DAC Registers loaded with all 0s.
V
IN
B = 6 V rms at 10 kHz sine wave,
V
IN
A = 0 V. DAC Registers loaded with all 0s.
Measured with input code transitions of all 0s to all 1s.
Measured between R
FB
A and OUT A or between
R
FB
B and OUT B.
V
IN
A = V
IN
B = 6 V rms at 1 kHz. DAC
Registers loaded with all 0s.
REV. 0
–3–
AD7112
ABSOLUTE MAXIMUM RATINGS*
V
DD
to AGND or DGND . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
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