530HB635M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 530HB635M000DG

530HB635M000DG: DescriptionCMOS/TTL Output Clock Oscillator, 635MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530HB635M000DG Overview

CMOS/TTL Output Clock Oscillator, 635MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530HB635M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	635 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Use LM3876T to connect to BTL power amplifier

Basic application circuit of LM31703

audio notch filter

Phase controlled temperature regulation circuit

Blue Medal 45-793241, 45-793246, 45-793247 instant electric water heater circuit diagram

Gain programmable buffer amplifier circuit for floating point conversion

Design and application of new switching power supply: Design and application of new switching power supply...; tonytong Power technology

Common indicators in the use of analog op amps: [i=s] This post was last edited by qwqwqw2088 on 2018-6-22 08:40 [/i] [size=4] Gain Bandwidth Product GBP: The product of the gain of the device and the specified bandwidth is an indicator for evaluat...; qwqwqw2088 Analogue and Mixed Signal

The mobile phone revolution has nothing to do with intelligence: [i=s]This post was last edited by jameswangsynnex on 2015-3-3 19:59[/i]　　Interconnect with set-top box 　　If the mobile phone becomes a "universal remote control" that can control all home appliances, ...; 探路者 Mobile and portable

[TI course sharing] MSP430 advanced - MSP430F5529 technical training: [i=s] This post was last edited by yejunjie176 on 2016-12-8 21:48 [/i] [align=left][color=#000][font=Arial, Helvetica, sans-serif][size=12px]Learning Topic: MSP430 Advanced - MSP430F5529 Technical Tra...; yejunjie176 TI Technology Forum

SRAM can only be written once! Repeated reading and writing help!: Hello everyone, I am a novice in FPGA. Recently, I am working on FPGA data collection and storage in external SRAM: IS61LV2568, and finally reading the data from SRAM and passing it to the microcontro...; xingdong2hao FPGA/CPLD

One week evaluation information delivered~: Good morning~~ The new week's evaluation information is here~~ Come and see what good activities and reports are coming~Activities in the application period: 1. Free review: ST MEMS waterproof pressur...; okhxyyo Special Edition for Assessment Centres

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components