5962-8753102TA datasheet, PDF - EEWORLD Datasheet

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5962-8753102TA: DescriptionFIFO, 512X9, 50ns, Asynchronous, CMOS, CDIP28, CERAMIC, DIP-28; Categorystorage storage; File Size128KB，17 Pages; ManufacturerTEMIC; Websitehttp://www.temic.de/

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5962-8753102TA Overview

FIFO, 512X9, 50ns, Asynchronous, CMOS, CDIP28, CERAMIC, DIP-28

5962-8753102TA Parametric

Parameter Name	Attribute value
Maker	TEMIC
package instruction	DIP,
Reach Compliance Code	unknown
Maximum access time	50 ns
Other features	RETRANSMIT
period time	65 ns
JESD-30 code	R-GDIP-T28
JESD-609 code	e0
memory density	4608 bit
memory width	9
Number of functions	1
Number of terminals	28
word count	512 words
character code	512
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	512X9
Exportable	NO
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Filter level	MIL-STD-883
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal location	DUAL
Base Number Matches	1

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REVISIONS

LTR

DESCRIPTION

DATE

APPROVED

Removed vendor CAGE 61772 as source of supply for case outline

letter Z, the F-11A package. Added case outline letters U and T, F-11

and D-15 to the drawing. Editorial changes throughout.

Changes in accordance with NOR 5962-R042-95.

Updated boilerplate to reflect current requirements. Corrections to

pages 4, 5, 8 and timing waveforms. - glg

1990 OCT 04

M. A. Frye

94-12-15

01-01-17

M. A. Frye

Raymond Monnin

THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED.

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

Kenneth Rice

CHECKED BY

Ray Monnin

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216

STANDARD

MICROCIRCUIT

DRAWING

THIS DRAWING IS AVAILABLE

FOR USE BY All DEPARTMENTS

APPROVED BY

Michael. A. Frye

MICROCIRCUITS, MEMORY, DIGITAL,

CMOS, PARALLEL 512 X 9 FIFO,

MONOLITHIC SILICON

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

AMSC N/A

DRAWING APPROVAL DATE

23 May 1988

REVISION LEVEL

SIZE

SHEET

CAGE CODE

67268

1 OF

5962-87531

DSCC FORM 2233

APR 97

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

5962-E172-01

2. APPLICABLE DOCUMENTS

2.1 Government specification, standards, and handbooks. The following specification, standards and handbooks form a part

of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the

issue listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto,

cited in the solicitation.

SPECIFICATION

DEPARTMENT OF DEFENSE

MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.

STANDARDS

DEPARTMENT OF DEFENSE

MIL-STD-883 - Test Method Standard Microcircuits.

MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.

HANDBOOKS

DEPARTMENT OF DEFENSE

MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMD's).

MIL-HDBK-780 - Standard Microcircuit Drawings.

(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization

Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the

text of this drawing shall take precedence. Nothing in this document, however, supersedes applicable laws and regulations

unless a specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-

JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer

Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-

38535 may be processed as QML product in accordance with the manufacturer's approved program plan and qualifying activity

approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make

modifications to the requirements herein. These modifications shall not affect the PIN as described herein. A "Q" or "QML"

certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified

in MIL-PRF-38535, appendix A and herein.

3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.

3.2.3 Truth table. The truth table shall be as specified on figure 2.

3.2.4 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection

provided that each coated microcircuit inspection lot (see MIL-PRF-38535, appendix A) shall be subjected to and pass the

Internal Water-Vapor Content test (test method 1018 of MIL-STD-883). The frequency of the internal water vapor testing may

not be decreased unless approved by the preparing activity.

3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are

as specified in table I and shall apply over the full case operating temperature range.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216-5000

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-87531

SHEET

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical

tests for each subgroup are described in table I.

3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed

in 1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). For

packages where the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not

marking the "5962-" on the device.

3.5.1 Certification/compliance mark. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535,

Appendix A.

3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an

approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to

listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535,

appendix A and the requirements herein.

3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided

with each lot of microcircuits delivered to this drawing.

3.8 Notification of change. Notification of change to DSCC-VA shall be required in accordance with MIL-PRF-38535,

appendix A.

3.9 Verification and review. DSCC, DSCC's agent and the acquiring activity retain the option to review the manufacturer's

facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the

reviewer.

4. QUALITY ASSURANCE PROVISIONS

4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A.

4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices

prior to quality conformance inspection. The following additional criteria shall apply:

a. Burn-in test (method 1015 of MIL-STD-883).

(1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level

control and shall be made available to the preparing or procuring activity upon request. The test circuit shall

specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in

test method 1015 of MIL-STD-883.

(2) T

= +125

C, minimum.

b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter

tests prior to burn-in are optional at the discretion of the manufacturer.

4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-

883 including groups A, B, C, and D inspections. The following additional criteria shall apply.

4.3.1 Group A inspection.

a. Tests shall be as specified in table II herein.

b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.

c. Subgroup 4 (C

and C

OUT

measurement) shall be measured only for the initial test and after any design or process

changes which may affect capacitance. Sample size is 15 devices with no failures, and all input and output terminals

tested.

d. Subgroups 7 and 8 tests shall include verification of the truth table.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216-5000

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-87531

SHEET

5962-8753102TA Related Products

	5962-8753102TA	5962-8753101TX	5962-8753101YX	5962-8753103YC	5962-8753101YC	5962-8753101TA	5962-8753103TA	5962-8753102YC
Description	FIFO, 512X9, 50ns, Asynchronous, CMOS, CDIP28, CERAMIC, DIP-28	FIFO, 512X9, 30ns, Asynchronous, CMOS, CDIP28, CERAMIC, DIP-28	FIFO, 512X9, 30ns, Asynchronous, CMOS,	FIFO, 512X9, 80ns, Asynchronous, CMOS,	FIFO, 512X9, 30ns, Asynchronous, CMOS,	FIFO, 512X9, 30ns, Asynchronous, CMOS, CDIP28, CERAMIC, DIP-28	FIFO, 512X9, 80ns, Asynchronous, CMOS, CDIP28, CERAMIC, DIP-28	FIFO, 512X9, 50ns, Asynchronous, CMOS, CQCC32, CERAMIC, LCC-32
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
Maximum access time	50 ns	30 ns	30 ns	80 ns	30 ns	30 ns	80 ns	50 ns
Other features	RETRANSMIT	RETRANSMIT	RETRANSMIT	RETRANSMIT	RETRANSMIT	RETRANSMIT	RETRANSMIT	RETRANSMIT
period time	65 ns	40 ns	40 ns	100 ns	40 ns	40 ns	100 ns	65 ns
memory density	4608 bit	4608 bit	4608 bit	4608 bit	4608 bit	4608 bit	4608 bit	4608 bit
memory width	9	9	9	9	9	9	9	9
Number of functions	1	1	1	1	1	1	1	1
word count	512 words	512 words	512 words	512 words	512 words	512 words	512 words	512 words
character code	512	512	512	512	512	512	512	512
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
organize	512X9	512X9	512X9	512X9	512X9	512X9	512X9	512X9
Exportable	NO	NO	NO	NO	NO	NO	NO	NO
Package body material	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP	DIP	QCCN	QCCN	QCCN	DIP	DIP	QCCN
Package form	IN-LINE	IN-LINE	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	IN-LINE	IN-LINE	CHIP CARRIER
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	NO	YES	YES	YES	NO	NO	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal form	THROUGH-HOLE	THROUGH-HOLE	NO LEAD	NO LEAD	NO LEAD	THROUGH-HOLE	THROUGH-HOLE	NO LEAD
Terminal location	DUAL	DUAL	QUAD	QUAD	QUAD	DUAL	DUAL	QUAD
Maker	TEMIC	-	-	TEMIC	TEMIC	TEMIC	TEMIC	TEMIC
package instruction	DIP,	DIP,	-	-	-	DIP,	DIP,	CERAMIC, LCC-32
JESD-30 code	R-GDIP-T28	R-GDIP-T28	-	-	-	R-GDIP-T28	R-GDIP-T28	R-CQCC-N32
JESD-609 code	e0	-	e4	e4	e4	e0	e0	e0
Number of terminals	28	28	-	-	-	28	28	32
Package shape	RECTANGULAR	RECTANGULAR	-	-	-	RECTANGULAR	RECTANGULAR	RECTANGULAR
Filter level	MIL-STD-883	MIL-STD-883	-	-	-	MIL-STD-883	MIL-STD-883	MIL-STD-883
Terminal surface	TIN LEAD	-	GOLD	GOLD	GOLD	TIN LEAD	TIN LEAD	TIN LEAD
Base Number Matches	1	1	1	1	1	1	-	-
length	-	37.211 mm	13.97 mm	13.97 mm	13.97 mm	37.211 mm	37.211 mm	13.97 mm
Maximum seat height	-	5.08 mm	3.048 mm	3.048 mm	3.048 mm	5.08 mm	5.08 mm	3.048 mm
Terminal pitch	-	2.54 mm	1.27 mm	1.27 mm	1.27 mm	2.54 mm	2.54 mm	1.27 mm
width	-	15.24 mm	11.43 mm	11.43 mm	11.43 mm	15.24 mm	15.24 mm	11.43 mm

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