5962L0053606VYC datasheet, PDF

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5962L0053606VYC: DescriptionStandard SRAM, 512KX8, 20ns, CMOS, CDFP36, CERAMIC, DFP-36; Categorystorage storage; File Size232KB，41 Pages; ManufacturerCobham PLC

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5962L0053606VYC Overview

Standard SRAM, 512KX8, 20ns, CMOS, CDFP36, CERAMIC, DFP-36

5962L0053606VYC Parametric

Parameter Name	Attribute value
Maker	Cobham PLC
package instruction	QFF, FL36,.6
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Maximum access time	20 ns
I/O type	COMMON
JESD-30 code	R-CDFP-F36
JESD-609 code	e4
length	25.4 mm
memory density	4194304 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	36
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
organize	512KX8
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFF
Encapsulate equivalent code	FL36,.6
Package shape	RECTANGULAR
Package form	FLATPACK
Parallel/Serial	PARALLEL
power supply	5 V
Certification status	Qualified
Filter level	MIL-PRF-38535 Class V
Maximum seat height	2.98 mm
Maximum standby current	0.045 A
Minimum standby current	4.5 V
Maximum slew rate	0.076 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	GOLD
Terminal form	FLAT
Terminal pitch	0.5 mm
Terminal location	DUAL
total dose	50k Rad(Si) V
width	15.24 mm
Base Number Matches	1

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REVISIONS

LTR

DESCRIPTION

Correction to TABLE I, I

parameter. Added Appendix B to allow for

the procurement of die. - glg

Correction to Appendix B, added paragraph 10.2.4 Die code. Updated

boilerplate references. ksr

Add 02 device representing an extended temperature device.

Corrected (SEP) effective with no latch-up in paragraph 1.5; was 90.5

MeV-cm

/mg changed to 80 MeV-cm

/mg ksr

Added devices 03 and 04, updated Table I.

ksr

DATE (YR-MO-DA)

00-12-11

APPROVED

Raymond Monnin

02-01-15

Raymond Monnin

02-10-22

Raymond Monnin

02-12-08

07-03-29

Raymond Monnin

Robert M. Heber

Added devices 05 and 06 updated Table I. Added case outline Y.

Boilerplate update, part of 5 year review. ksr

Corrected Table I, the post radiation limit for I

DD2

for devices 05 and

06. ksr

Made corrections to case U dimension table symbol A, D, E1, and E2.

ksr

07-04-11

09-09-24

Robert M. Heber

Charles F. Saffle

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

Gary L. Gross

CHECKED BY

Jeff Bowling

STANDARD

MICROCIRCUIT

DRAWING

THIS DRAWING IS AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

http://www.dscc.dla.mil

APPROVED BY

Raymond Monnin

DRAWING APPROVAL DATE

00-09-19

REVISION LEVEL

MICROCIRCUIT, MEMORY, DIGITAL,

CMOS, 512K x 8-BIT, RADIATION-

HARDENED SRAM, MONOLITHIC

SILICON

SIZE

SHEET

AMSC N/A

CAGE CODE

67268

1 OF

5962-00536

5962-E222-09

DSCC FORM 2233

APR 97

DEPARTMENT OF DEFENSE HANDBOOKS

MIL-HDBK-103 -

MIL-HDBK-780 -

List of Standard Microcircuit Drawings.

Standard Microcircuit Drawings.

(Copies of these documents are available online at

http://assist.daps.dla.mil/quicksearch/

or from the Standardization Document

Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.

Unless otherwise specified, the issues of these documents are those cited in the solicitation.

AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)

ASTM Standard F1192

Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by

Heavy Ion Irradiation of Semiconductor Devices.

(Applications for copies of ASTM publications should be addressed to:

ASTM International, PO Box C700, 100 Barr

Harbor Drive, West Conshohocken, PA 19428-2959;

http://www.astm.org.)

(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization

Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

ELECTRONICS INDUSTRIES ASSOCIATION (EIA)

JEDEC Standard EIA/JESD78

IC Latch-Up Test.

(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA

22201;

http://www.jedec.org.)

(Non-Government standards and other publications are normally available from the organizations that prepare or distribute the

documents. These documents also may be available in or through libraries or other informational services.)

2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of

this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless

a specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q, T and V shall be in accordance with MIL-PRF-

38535, and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in

the QM plan shall not effect the form, fit, or function as described herein. The individual item requirements for device class M

shall be in accordance with MIL-PRF-38535, appendix A and as specified herein.

3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix B to this document.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in

MIL-PRF-38535 and herein for device classes Q, T and V or MIL-PRF-38535, appendix A and herein for device class M.

3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 and figure 1 herein.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.

3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3.

3.2.4 Output load circuit. The output load circuit shall be as specified on figure 4.

3.2.5 Timing waveforms. The timing waveforms shall be as specified on figure 5.

3.2.6 Radiation test circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision

control and shall be made available to the preparing and acquiring activity upon request.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-00536

SHEET

3.2.7 Functional tests. Various functional tests used to test this device are contained in appendix A. If the test patterns

cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed.

For device class M, alternate test patterns shall be maintained under document revision level control by the manufacturer and

shall be made available to the preparing or acquiring activity upon request. For device classes Q, T and V, alternate test

patterns shall be under the control of the device manufacturer’s Technology Review Board (TRB) in accordance with MIL-PRF-

38535 and shall be made available to the preparing or acquiring activity upon request.

3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and post-irradiation parameter limits are as specified in table I and shall apply over the full

case operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical

tests for each subgroup are defined in table I.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be

marked. Marking for device classes Q, T, and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall

be in accordance with MIL-PRF-38535, appendix A.

3.5.1 Certification/compliance mark. The certification mark for device classes Q, T and V shall be a "QML" or "Q" as required

in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.

3.6 Certificate of compliance. For device classes Q, T and V, a certificate of compliance shall be required from a QML-38535

listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of

compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see

6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this

drawing shall affirm that the manufacturer's product meets, for device classes Q, T and V, the requirements of MIL-PRF-38535

and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.

3.7 Certificate of conformance. A certificate of conformance as required for device classes Q, T and V in MIL-PRF-38535 or

for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.

3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2

herein) involving devices acquired to this drawing is required for any change that affects this drawing.

3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the

option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made

available onshore at the option of the reviewer.

3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in

microcircuit group number 41 (see MIL-PRF-38535, appendix A).

4. VERIFICATION

4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with

MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan

shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in

accordance with MIL-PRF-38535, appendix A.

For device class T, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 and the device

manufacturer's QM plan, including screening, qualification, and conformance inspection. The performance envelope and

reliability information shall be as specified in the manufacturers QM plan.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-00536

SHEET

5962L0053606VYC Related Products

	5962L0053606VYC	5962L0053606VYA	5962L0053605VYC
Description	Standard SRAM, 512KX8, 20ns, CMOS, CDFP36, CERAMIC, DFP-36	Standard SRAM, 512KX8, 20ns, CMOS, CDFP36, CERAMIC, DFP-36	Standard SRAM, 512KX8, 20ns, CMOS, CDFP36, CERAMIC, DFP-36
Maker	Cobham PLC	Cobham PLC	Cobham PLC
package instruction	QFF, FL36,.6	QFF, FL36,.6	QFF, FL36,.6
Reach Compliance Code	unknown	unknown	unknown
ECCN code	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C
Maximum access time	20 ns	20 ns	20 ns
I/O type	COMMON	COMMON	COMMON
JESD-30 code	R-CDFP-F36	R-CDFP-F36	R-CDFP-F36
JESD-609 code	e4	e0	e4
length	25.4 mm	25.4 mm	25.4 mm
memory density	4194304 bit	4194304 bit	4194304 bit
Memory IC Type	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
memory width	8	8	8
Number of functions	1	1	1
Number of terminals	36	36	36
word count	524288 words	524288 words	524288 words
character code	512000	512000	512000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-55 °C
organize	512KX8	512KX8	512KX8
Output characteristics	3-STATE	3-STATE	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFF	QFF	QFF
Encapsulate equivalent code	FL36,.6	FL36,.6	FL36,.6
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	FLATPACK	FLATPACK
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL
power supply	5 V	5 V	5 V
Certification status	Qualified	Qualified	Qualified
Filter level	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V
Maximum seat height	2.98 mm	2.98 mm	2.98 mm
Maximum standby current	0.045 A	0.045 A	0.045 A
Minimum standby current	4.5 V	4.5 V	4.5 V
Maximum slew rate	0.076 mA	0.076 mA	0.076 mA
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	MILITARY
Terminal surface	GOLD	TIN LEAD	GOLD
Terminal form	FLAT	FLAT	FLAT
Terminal pitch	0.5 mm	0.5 mm	0.5 mm
Terminal location	DUAL	DUAL	DUAL
total dose	50k Rad(Si) V	50k Rad(Si) V	50k Rad(Si) V
width	15.24 mm	15.24 mm	15.24 mm
Base Number Matches	1	1	-

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