85C72/82/92
1K/2K/4K 5.0V CMOS Serial EEPROM
FEATURES
•
•
•
•
•
•
•
•
•
•
Low power CMOS technology
Two wire serial interface bus, I
2
C
™
compatible
5 volt only operation
Self-timed write cycle (including auto-erase)
Page-write buffer
1ms write cycle time for single byte
1,000,000 ERASE/WRITE cycles guaranteed
Data retention >200 years
8-pin DIP or SOIC package
Available for extended temperature ranges:
- Commercial: 0˚C to +70˚C
- Industrial: -40˚C to +85˚C
- Automotive: -40˚C to +125˚C
PACKAGE TYPE
DIP
A0
A1
A2
V
SS
1
2
3
4
8
V
CC
NC
SCL
SDA
85C72
85C82
85C92
7
6
5
8-lead
SOIC
A0
A1
A2
1
2
3
4
8
V
CC
NC
SCL
SDA
85C72
85C82
85C92
7
6
5
85C72
Organization
Page Write
Buffer
128 x 8
2 Bytes
85C82
256 x 8
2 Bytes
85C92
2 x 256 x 8
8 Bytes
14-lead
SOIC
V
SS
NC
A0
1
2
3
4
5
6
7
14
13
12
NC
V
CC
NC
NC
SCL
SDA
NC
DESCRIPTION
The Microchip Technology Inc. 85C72/82/92 is a 1K/
2K/4K bit Electrically Erasable PROM. The device is
organized as shown with a two wire serial interface.
Advanced CMOS technology allows a significant
reduction in power over NMOS serial devices. The
85C72/82/92 also has a page-write capability for up to
8 bytes of data (see chart). Up to eight 85C72/82/92s
may be connected to the two wire bus. The 85C72/82/
92 is available in standard 8-pin DIP and surface mount
SOIC packages.
A1
NC
A2
V
SS
NC
85C92
11
10
9
8
BLOCK DIAGRAM
DATA
BUFFER
(FIF0)
DATA REG.
SDA
V
CC
V
SS
V
PP
R/W AMP
SLAVE ADR.
AP
DO
MEMORY
D I
RN
ARRAY
E T A0 to
S E A7
SR
INCREMENT
SCL
CONTROL
LOGIC
A0 A1 A2
I
2
C is a trademark of Philips Corporation
©
1995 Microchip Technology Inc.
DS11182C-page 1
85C72/82/92
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name
A0, A1, A2
V
SS
SDA
SCL
NC
V
CC
PIN FUNCTION TABLE
Function
Chip Address Inputs
Ground
Serial Address/Data Input/Output
Serial Clock
No Connect
+5V Power Supply
V
CC
........................................................................ 7.0V
All inputs and outputs w.r.t. V
SS
....-0.6V to V
CC
+1.0V
Storage temperature ...........................-65˚C to +150˚C
Ambient temp. with power applied ......-65˚C to +125˚C
Soldering temperature of leads (10 seconds) ...+300˚C
ESD protection on all pins..................................... 4 kV
*Notice:
Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
Commercial
Industrial
Automotive
Symbol
V
TH
V
IH
V
IL
V
OL
V
IH
V
IL
I
LI
I
LO
C
IN
,
C
OUT
I
CCO
Min
2.8
V
CC
x 0.7
-0.3
Max
4.5
V
CC
+ 1
V
CC X
0.3
0.4
V
CC
- 0.5 V
CC
+ 0.5
-0.3
—
—
—
—
0.5
10
10
7.0
3.5
4.25
(C):
(I):
(E):
Units
V
V
V
V
V
V
µ
A
µ
A
pF
mA
mA
µ
A
µ
A
V
IN
= 0V
TO
Vcc
V
OUT
= 0V
TO
Vcc
V
IN
/V
OUT
= 0V (Note 1)
Tamb = +25˚C, f = 1 MHz
F
CLK
= 100 kHz, program cycle time = 1 ms,
V
CC
= 5V, Tamb = 0˚C to +70˚C
F
CLK
= 100 kHz, program cycle time = 1 ms,
V
CC
= 5V, Tamb = (I) and (E)
V
CC
= 5V, Tamb = (C), (I) and (E)
SDA=SCL=V
CC
=5V (no PROGRAM active)
I
OL
= 3.2 mA (SDA 0nly)
Tamb = 0˚C to +70˚C
Tamb = -40˚C to +85˚C
Tamb = -40˚C to 125˚C
Conditions
V
CC
= +5V (10%)
Parameter
V
CC
detector threshold
SCL and SDA pins:
High level input voltage
Low level input voltage
Low level output voltage
A0, A1 & A2 pins:
HIgh level input voltage
Low level input voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
Operating current
read cycle
Standby current
I
CCR
I
CCS
—
—
750
100
Note 1: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
BUS TIMING START/STOP
V
HYS
SCL
T
SU:STA
SDA
T
HD:STA
T
SU:STO
START
STOP
DS11182C-page 2
©
1995 Microchip Technology Inc.
85C72/82/92
TABLE 1-3:
AC CHARACTERISTICS
Parameter
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
START condition setup time
Data input hold time
Data input setup time
Data output delay time
STOP condition setup time
Bus free time
Symbol
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD:STA
T
SU:STA
T
HD
:
DAT
T
SU
:
DAT
T
PD
T
SU
:
STO
T
BUF
Min
—
4000
4700
—
—
4000
4700
0
250
300
4700
4700
Typ
—
—
—
—
—
—
—
—
—
—
—
—
Max
100
—
—
1000
300
—
—
—
—
3500
—
—
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Time the bus must be free
before a new transmission
can start
Note 1
After this period the first
clock pulse is generated
Only relevant for repeated
START condition
Remarks
Input filter time constant
(SDA and SCL pins)
Program cycle time
T
I
T
WC
—
—
—
.4
.4N
100
1
N
ns
ms
ms
Byte Mode
Page Mode, N = # of bytes
to be written
Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
FIGURE 1-2:
BUS TIMING DATA
t
F
t
HIGH
t
LOW
t
R
SCL
t
SU:STA
t
HD:STA
SDA
IN
t
AA
SDA
OUT
t
AA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
BUF
©
1995 Microchip Technology Inc.
DS11182C-page 3
85C72/82/92
2.0
FUNCTIONAL DESCRIPTION
3.3
Stop Data Transfer (C)
The 85C72/82/92 supports a bidirectional two wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions, while the
85C72/82/92 works as slave. Both, master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated.
Up to eight 85C72/82/92s can be connected to the bus,
selected by the A0, A1 and A2 chip address inputs.
Other devices can be connected to the bus, but require
different device codes than the 85C72/82/92 (refer to
section Slave Address).
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a start condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.
3.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 85C72/82/92 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case the slave must leave the data line HIGH to enable
the master to generate the STOP condition
FIGURE 3-1:
(A)
SCL
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D)
(D)
(C)
(A)
SDA
START CONDITION
ADDRESS
DATA ALLOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID
STOP
CONDITION
DS11182C-page 4
©
1995 Microchip Technology Inc.
85C72/82/92
4.0
SLAVE ADDRESS
5.0
BYTE PROGRAM MODE
The chip address inputs A0, A1 and A2 of each 85C72/
82/92 must be externally connected to either V
CC
or
ground (V
SS
), assigning to each 85C72/82/92 a unique
3-bit address. Up to eight 85C72/82/92s may be con-
nected to the bus. Chip selection is then accomplished
through software by setting the bits A0, A1 and A2 of
the transmitted slave address to the corresponding
hardwired logic levels of the selected 85C72/82/92.
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 85C72/82/92, followed by the chip
address bits A0, A1 and A2. In the 85C92 the seventh
bit of that byte (BA) is used to select the upper block
(addresses 100 - 1FF) or the lower block (000 - FFF) of
the array.
The eighth bit of slave address determines if the master
device wants to read or write to the 85C72/82/92 (see
Figure 4-1).
The 85C72/82/92 monitors the bus for its correspond-
ing slave address all the time. It generates an acknowl-
edge bit if the slave address was true and it is not in a
programming mode.
In this mode, the master sends addresses and one
data byte to the 85C72/82/92.
Following the START condition, the device code (4-bit),
the slave address (3-bit), and the R/W bit, which is logic
LOW, are placed onto the bus by the master. This indi-
cates to the addressed 85C72/82/92 that a byte with a
word address will follow after it has generated an
acknowledge bit. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 85C72/82/92. After
receiving the acknowledge of the 85C72/82/92, the
master device transmits the data word to be written into
the addressed memory location. The 85C72/82/92
acknowledges again and the master generates a
STOP condition. This initiates the internal program-
ming cycle of the 85C72/82/92 (see Figure 6-1).
6.0
PAGE PROGRAM MODE
FIGURE 4-1:
SLAVE ADDRESS
ALLOCATION
READ/WRITE
START
SLAVE ADDRESS
R/W
A
1
0
1
0
A2
A1
A0
To program the 85C72/82/92, the master sends
addresses and data to the 85C72/82/92 which is the
slave (see Figure 6-1). This is done by supplying a
START condition followed by the 4-bit device code, the
3-bit slave address, and the R/W bit which is defined as
a logic LOW for a write. This indicates to the addressed
slave that a word address will follow so the slave out-
puts the acknowledge pulse to the master during the
ninth clock pulse. When the word address is received
by the 85C72/82/92, it places it in the lower 8 bits of the
address pointer defining which memory location is to
be written. The 85C72/82/92 will generate an acknowl-
edge after every 8 bits received and store them con-
secutively in a 2-byte RAM until a stop condition is
detected which initiates the internal programming
cycle. If more than 2 bytes are transmitted by the mas-
ter, the 85C72/82/92 will terminate the write cycle. This
does not affect erase/write cycles of the EEPROM
array.
If the master generates a STOP condition after trans-
mitting the first data word (Point ‘P’ on Figure 6-1), byte
programming mode is entered.
The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received (up to two) data bytes will
be written in a serial manner.
The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data bytes (N max = 2).
FIGURE 6-1:
PROGRAM MODE (ERASE/WRITE)
ACKNOWLEDGES FROM SLAVE
START
SLAVE
ADDRESS
0 A
WORD
ADDRESS
A
DATA BYTE 1
A
DATA BYTE N
A STOP
R/W
P
©
1995 Microchip Technology Inc.
DS11182C-page 5
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