5962-9471201MYC datasheet, PDF

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5962-9471201MYC: DescriptionField Programmable Gate Array, CMOS, CQFP100, TOP BRAZED, CERAMIC, QFP-100; CategoryProgrammable logic devices Programmable logic; File Size99KB，15 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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5962-9471201MYC Overview

Field Programmable Gate Array, CMOS, CQFP100, TOP BRAZED, CERAMIC, QFP-100

5962-9471201MYC Parametric

Parameter Name	Attribute value
Maker	XILINX
Parts packaging code	QFP
package instruction	GQFF,
Contacts	100
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
JESD-30 code	S-CQFP-F100
JESD-609 code	e4
length	19.05 mm
Number of terminals	100
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	GQFF
Package shape	SQUARE
Package form	FLATPACK, GUARD RING
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Filter level	MIL-STD-883
Maximum seat height	3.429 mm
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	FLAT
Terminal pitch	0.65 mm
Terminal location	QUAD
width	19.05 mm
Base Number Matches	1

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XC4000A

Logic Cell Array Family

Product Specifications

Features

Description

The XC4000A family of FPGAs offers four devices at the low

end of the XC4000 family complexity range. XC4000A

differs from XC4000 in four areas: fewer routing resources,

fewer wide-edge decoders, higher output sink current, and

improved output slew-rate control.

•

Third Generation Field-Programmable Gate Arrays

–

Abundant flip-flops

Flexible function generators

On-chip ultra-fast RAM

Dedicated high-speed carry-propagation circuit

Wide edge decoders (two per edge)

Hierarchy of interconnect lines

Internal 3-state bus capability

Eight global low-skew clock or signal distribution

network

•

The XC4000 routing structure is optimized for smaller

designs, naturally requiring fewer routing resources. The

XC4000A devices have four Longlines and four single-

length lines per row and column, while the XC4000

devices have six Longlines and eight single-length lines

per row and column. This results in a smaller chip area

and lower cost per device.

•

Flexible Array Architecture

– Programmable logic blocks and I/O blocks

– Programmable interconnects and wide decoders

•

XC4000A has two wide-edge decoders on every device

edge, while the XC4000 has four. All other wide-decoder

features are identical in XC4000 and XC4000A.

•

Sub-micron CMOS Process

– High-speed logic and Interconnect

– Low power consumption

•

XC4000A outputs are specified at 24 mA, sink current,

while XC4000 outputs are specified at 12 mA. The source

current is the same 4 mA for both families.

•

Systems-Oriented Features

–

IEEE 1149.1-compatible boundary-scan logic support

Programmable output slew rate (4 modes)

Programmable input pull-up or pull-down resistors

24-mA sink current per output (48 per pair)

•

The XC4000A family offers a more sophisticated output

slew-rate control structure with four configurable options

for each individual output driver: fast, medium fast, me-

dium slow, and slow. Slew-rate control can alleviate

ground-bounce problems when multiple outputs switch

simultaneously, and it can reduce or eliminate crosstalk

and transmission-line effects on printed circuit boards.

Note that the XC4003 and XC4005 devices are available in

both flavors, the lower-priced XC4003A/XC4005A with re-

duced routing, and the higher-priced XC4003/XC4005 with

more abundant routing resources. The XC4000A devices

are intended for less demanding and more structured

designs, and the XC4000 devices for more random designs

requiring additional routing resources.

The equivalent devices are pin-compatible and are avail-

able in identical packages, but they are not bitstream

compatible. In order to move from a XC4000A to a XC4000,

or vice versa, the design must be recompiled.

•

Configured by Loading Binary File

– Unlimited reprogrammability

– Six programming modes

•

XACT Development System runs on ’386/’486-type PC,

NEC PC, Apollo, Sun-4, and Hewlett-Packard 700 Series

– Interfaces to popular design environments like

Viewlogic, Mentor Graphics and OrCAD

– Fully automatic partitioning, placement and routing

– Interactive design editor for design optimization

– 288 macros, 34 hard macros, RAM/ROM compiler

Table 1. The XC4000A Family of Field-Programmable Gate Arrays

Device

Appr. Gate Count

CLB Matrix

Number of CLBs

Number of Flip-Flops

Max Decode Inputs (per side)

Max RAM Bits

Number of IOBs

XC4002A

2,000

8x8

256

2,048

XC4003A

3,000

10 x 10

100

360

3,200

XC4004A

4,000

12 x 12

144

480

4,608

XC4005A

5,000

14 x 14

196

616

6,272

112

2-71

5962-9471201MYC Related Products

	5962-9471201MYC	5962-9471201MXC	5962-9471202MZC	5962-9471201MZC	5962-9471202MYC
Description	Field Programmable Gate Array, CMOS, CQFP100, TOP BRAZED, CERAMIC, QFP-100	Field Programmable Gate Array, CMOS, CPGA120, CERAMIC, PGA-120	Field Programmable Gate Array, CMOS, CQFP100, TOP BRAZED, CERAMIC, QFP-100	Field Programmable Gate Array, CMOS, CQFP100, TOP BRAZED, CERAMIC, QFP-100	Field Programmable Gate Array, CMOS, CQFP100, TOP BRAZED, CERAMIC, QFP-100
Maker	XILINX	XILINX	XILINX	XILINX	XILINX
Parts packaging code	QFP	PGA	QFP	QFP	QFP
package instruction	GQFF,	PGA,	GQFF,	GQFF,	GQFF,
Contacts	100	120	100	100	100
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown
ECCN code	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C
JESD-30 code	S-CQFP-F100	S-CPGA-P120	S-CQFP-F100	S-CQFP-F100	S-CQFP-F100
JESD-609 code	e4	e4	e4	e4	e4
length	19.05 mm	34.544 mm	19.05 mm	19.05 mm	19.05 mm
Number of terminals	100	120	100	100	100
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	GQFF	PGA	GQFF	GQFF	GQFF
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, GUARD RING	GRID ARRAY	FLATPACK, GUARD RING	FLATPACK, GUARD RING	FLATPACK, GUARD RING
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Filter level	MIL-STD-883	MIL-STD-883	MIL-STD-883	MIL-STD-883	MIL-STD-883
Maximum seat height	3.429 mm	4.318 mm	3.429 mm	3.429 mm	3.429 mm
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V
surface mount	YES	NO	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal surface	GOLD	GOLD	GOLD	GOLD	GOLD
Terminal form	FLAT	PIN/PEG	FLAT	FLAT	FLAT
Terminal pitch	0.65 mm	2.54 mm	0.65 mm	0.65 mm	0.65 mm
Terminal location	QUAD	PERPENDICULAR	QUAD	QUAD	QUAD
width	19.05 mm	34.544 mm	19.05 mm	19.05 mm	19.05 mm
Base Number Matches	1	1	1	1	1

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