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IDT7132SA25JG

Description
Dual-Port SRAM, 2KX8, 25ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52
Categorystorage    storage   
File Size138KB,16 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
Download Datasheet Parametric View All

IDT7132SA25JG Overview

Dual-Port SRAM, 2KX8, 25ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52

IDT7132SA25JG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeLCC
package instructionQCCJ, LDCC52,.8SQ
Contacts52
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time25 ns
Other featuresAUTOMATIC POWER DOWN
I/O typeCOMMON
JESD-30 codeS-PQCC-J52
JESD-609 codee3
length19.1262 mm
memory density16384 bit
Memory IC TypeDUAL-PORT SRAM
memory width8
Humidity sensitivity level1
Number of functions1
Number of ports2
Number of terminals52
word count2048 words
character code2000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize2KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC52,.8SQ
Package shapeSQUARE
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply5 V
Certification statusNot Qualified
Maximum seat height4.572 mm
Maximum standby current0.015 A
Minimum standby current4.5 V
Maximum slew rate0.22 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width19.1262 mm
Base Number Matches1
HIGH SPEED
2K x 8 DUAL PORT
STATIC RAM
IDT7132SA/LA
IDT7142SA/LA
Features
High-speed access
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25ns (max.)
– Military: 25/35/55/100ns (max.)
Low-power operation
– IDT7132/42SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
– IDT7132/42LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
MASTER IDT7132 easily expands data bus width to 16-or-more
bits using SLAVE IDT7142
On-chip port arbitration logic (IDT7132 only)
BUSY
output flag on IDT7132;
BUSY
input on IDT7142
Battery backup operation —2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC
packages
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
OL-
I/O
7L
I/O
Control
I/O
Control
I/O
OR-
I/O
7R
m
BUSY
L
(1,2)
A
10L
A
0L
Address
Decoder
11
BUSY
R
(1,2)
MEMORY
ARRAY
11
Address
Decoder
A
10R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
LOGIC
CE
R
OE
R
R/W
R
2692 drw 01
NOTES:
1. IDT7132 (MASTER):
BUSY
is open drain output and requires pullup resistor of 270Ω.
IDT7142 (SLAVE):
BUSY
is input.
2. Open drain output: requires pullup resistor of 270Ω.
OCTOBER 2008
1
©2008 Integrated Device Technology, Inc.
DSC-2692/18
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