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7009L15PFI

Description
SRAM
Categorystorage    storage   
File Size143KB,17 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

7009L15PFI Overview

SRAM

7009L15PFI Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
package instruction,
Reach Compliance Codenot_compliant
JESD-609 codee0
Humidity sensitivity level3
Terminal surfaceTin/Lead (Sn85Pb15)
Base Number Matches1
HIGH-SPEED
128K x 8 DUAL-PORT
STATIC RAM
Features
x
x
x
IDT7009L
x
x
x
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15/20ns (max.)
Low-power operation
– IDT7009L
Active: 1W (typ.)
Standby: 1mW (typ.)
Dual chip enables allow for depth expansion without
external logic
IDT7009 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device
x
x
x
x
x
x
x
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/W
L
CE
0L
CE
1L
OE
L
R/W
R
CE
0R
CE
1R
OE
R
I/O
0-7L
I/O
Control
I/O
Control
I/O
0-7R
BUSY
L
A
16L
A
0L
(1,2)
BUSY
R
128Kx8
MEMORY
ARRAY
7009
17
17
(1,2)
Address
Decoder
Address
Decoder
A
16R
A
0R
CE
0L
CE
1L
OE
L
R/W
L
SEM
L
(2)
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
0R
CE
1R
OE
R
R/W
R
SEM
R
(2)
INT
R
4839 drw 01
M/S
(1)
NOTES:
1.
BUSY
is an input as a Slave (M/S = V
IL
) and an output when it is a Master (M/S = V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
JANUARY 2001
DSC-4839/2
1
©2000 Integrated Device Technology, Inc.
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