7005L35FGB8 datasheet, PDF - EEWORLD Datasheet

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7005L35FGB8: DescriptionDual-Port SRAM, 8KX8, 35ns, CMOS, PQFP68, 0.970 X 0.970 INCH, 0.080 INCH HEIGHT, GREEN, QFP-68; Categorystorage storage; File Size358KB，21 Pages; ManufacturerIDT (Integrated Device Technology)

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7005L35FGB8 Overview

Dual-Port SRAM, 8KX8, 35ns, CMOS, PQFP68, 0.970 X 0.970 INCH, 0.080 INCH HEIGHT, GREEN, QFP-68

7005L35FGB8 Parametric

Parameter Name	Attribute value
Maker	IDT (Integrated Device Technology)
package instruction	QFF,
Reach Compliance Code	compliant
Maximum access time	35 ns
JESD-30 code	S-PQFP-F68
JESD-609 code	e3
length	24.2062 mm
memory density	65536 bit
Memory IC Type	DUAL-PORT SRAM
memory width	8
Number of functions	1
Number of terminals	68
word count	8192 words
character code	8000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	8KX8
Package body material	PLASTIC/EPOXY
encapsulated code	QFF
Package shape	SQUARE
Package form	FLATPACK
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	MATTE TIN
Terminal form	FLAT
Terminal pitch	0.8 mm
Terminal location	QUAD
width	24.2062 mm
Base Number Matches	1

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HIGH-SPEED

8K x 8 DUAL-PORT

STATIC RAM

Features

◆

IDT7005S/L

◆

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

– Military: 20/25/35/55/70ns (max.)

– Industrial: 35/55ns (max.)

– Commercial:15/17/20/25/35/55ns (max.)

Low-power operation

– IDT7005S

Active: 750mW (typ.)

Standby: 5mW (typ.)

– IDT7005L

Active: 700mW (typ.)

Standby: 1mW (typ.)

IDT7005 easily expands data bus width to 16 bits or more

using the Master/Slave select when cascading more than

one device

◆

M/S = H for BUSY output flag on Master,

M/S = L for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Devices are capable of withstanding greater than 2001V

electrostatic discharge

Battery backup operation—2V data retention

TTL-compatible, single 5V (±10%) power supply

Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin

thin quad flatpack

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

Functional Block Diagram

R/W

I/O

- I/O

I/O

Control

BUSY

12L

(1,2)

I/O

-I/O

I/O

Control

BUSY

Address

Decoder

(1,2)

MEMORY

ARRAY

Address

Decoder

12R

R/W

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

(2)

INT

NOTES:

1. (MASTER):

BUSY

is output; (SLAVE):

BUSY

is input.

BUSY

outputs and

INT

outputs are non-tri-stated push-pull.

M/S

SEM

INT

(2)

2738 drw 01

SEPTEMBER 2012

DSC 2738/17

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