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8S73034AMILFT

Description
SOIC-16, Reel
Categorylogic    logic   
File Size1MB,21 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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8S73034AMILFT Overview

SOIC-16, Reel

8S73034AMILFT Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeSOIC
package instructionSOP, SOP16,.25
Contacts16
Manufacturer packaging codeDCG16
Reach Compliance Codecompliant
ECCN codeEAR99
series8S
Input adjustmentDIFFERENTIAL LATCHED
JESD-30 codeR-PDSO-G16
JESD-609 codee3
length9.9 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level3
Number of functions1
Number of inverted outputs
Number of terminals16
Actual output times3
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
power supply2.5/3.3 V
Prop。Delay @ Nom-Sup0.565 ns
propagation delay (tpd)0.51 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.05 ns
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)3.8 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9 mm
minfmax1600 MHz
Base Number Matches1
Low Skew,
÷
2
, ÷
4
, ÷
8 Differential-to-LVPECL
Clock Divider
ICS8S73034I
DATA SHEET
General Description
The ICS8S73034I is a high-speed, differential-to- LVPECL clock
divider designed for high-performance telecommunication,
computing and networking applications. High clock frequency
capability and the differential design make the ICS8S73034I an ideal
choice for performance clock distribution networks. The device
frequency-divides the input clock by ÷2, ÷4 and ÷8. Each
frequency-divided clock signal is output at a separate LVPECL
output. The differential input pair can be driven by LVPECL, LVDS,
CML and SSTL signals. Single-ended input signals are supported by
using the integrated bias voltage generator (V
BB
). The ICS8S73034I
is optimized for 3.3V and 2.5V power supply voltages and the
temperature range of -40 to +85°C. The device is available in
space-saving 16-lead TSSOP and SOIC packages.
Features
÷2, ÷4 and ÷8 clock frequency divider
Three differential LVPECL output pairs
One differential PCLK, nPCLK input pair
PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, LVDS, CML
V
BB
bias voltage generator supports single-ended LVPECL clock
input signals
LVCMOS control inputs
Maximum input frequency: 3.2GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with bias resistors on nPCLK input
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
nEN
Pulldown
Pin Assignment
D
Q
LE
÷2
R
÷4
R
Q1
nQ1
Q0
nQ0
Q0
nQ0
V
CC
Q1
nQ1
V
CC
Q2
nQ2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
nEN
nc
PCLK
nPCLK
V
BB
MR
V
EE
PCLK
Pulldown
nPCLK
Pullup/Pulldown
VBB
÷8
R
MR
Pulldown
Q2
nQ2
ICS8S73034I
16-Lead SOIC, 150 Mil
3.9mm x 9.9mm x 1.375mm package body
M Package
Top View
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
ICS8S73034AMI REVISION A JUNE 8, 2011
1
©2011 Integrated Device Technology, Inc.

8S73034AMILFT Related Products

8S73034AMILFT 8S73034AGILFT
Description SOIC-16, Reel TSSOP-16, Reel
Brand Name Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code SOIC TSSOP
package instruction SOP, SOP16,.25 TSSOP, TSSOP16,.25
Contacts 16 16
Manufacturer packaging code DCG16 PGG16
Reach Compliance Code compliant compliant
ECCN code EAR99 EAR99
series 8S 8S
Input adjustment DIFFERENTIAL LATCHED DIFFERENTIAL LATCHED
JESD-30 code R-PDSO-G16 R-PDSO-G16
JESD-609 code e3 e3
length 9.9 mm 5 mm
Logic integrated circuit type LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER
Humidity sensitivity level 3 1
Number of functions 1 1
Number of terminals 16 16
Actual output times 3 3
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP TSSOP
Encapsulate equivalent code SOP16,.25 TSSOP16,.25
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260
power supply 2.5/3.3 V 2.5/3.3 V
Prop。Delay @ Nom-Sup 0.565 ns 0.565 ns
propagation delay (tpd) 0.51 ns 0.51 ns
Certification status Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.05 ns 0.05 ns
Maximum seat height 1.75 mm 1.2 mm
Maximum supply voltage (Vsup) 3.8 V 3.8 V
Minimum supply voltage (Vsup) 2.375 V 2.375 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V
surface mount YES YES
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed
Terminal form GULL WING GULL WING
Terminal pitch 1.27 mm 0.65 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED 30
width 3.9 mm 4.4 mm
minfmax 1600 MHz 1600 MHz
Base Number Matches 1 1
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