8743004DKILF datasheet, PDF - EEWORLD Datasheet

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8743004DKILF: DescriptionPLL Based Clock Driver, 8743004 Series, 4 True Output(s), 0 Inverted Output(s), 6 X 6 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220, VFQFN-40; Categorylogic logic; File Size1MB，27 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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8743004DKILF Overview

PLL Based Clock Driver, 8743004 Series, 4 True Output(s), 0 Inverted Output(s), 6 X 6 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220, VFQFN-40

8743004DKILF Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFN
package instruction	HVQCCN,
Contacts	40
Reach Compliance Code	compliant
ECCN code	EAR99
series	8743004
Input adjustment	DIFFERENTIAL MUX
JESD-30 code	S-XQCC-N40
JESD-609 code	e3
length	6 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	40
Actual output times	4
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	OPEN-EMITTER
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	6 mm
minfmax	160 MHz
Base Number Matches	1

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PRELIMINARY

FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/

CLOCK GENERATOR FOR PCI EXPRESS™ AND ETHERNET

ICS8743004I

General Description

The ICS8743004I is Zero-Delay Buffer/Frequency

Multiplier with four differential LVDS or LVPECL

HiPerClockS™

output pairs (pin selectable output type), and uses

external feedback for “zero delay” clock

regeneration. In PCI Express and Ethernet

applications, 100MHz and 125MHz are the most commonly used

reference clock frequencies and each of the four output pairs can

be independently set for either 100MHz or 125MHz. With an

output frequency range of 98MHz to 165MHz, the device is also

suitable for use in a variety of other applications such as Fibre

Channel (106.25MHz) and XAUI (156.25MHz). The M-LVDS

Input/Output pair is useful in backplane applications when the

reference clock can either be local (on the same board as the

ICS8743004I) or remote via a backplane connector. In output

mode, an input from a local reference clock applied to the

CLK/nCLK input pins is translated to M-LVDS and driven out to the

MLVDS/nMLVDS pins. In input mode, the internal M_LVDS driver

is placed in Hi-Z state using the OE_MLVDS pin and

MLVDS/nMLVDS pin then becomes an input (e.g. from a

backplane).

Features

•

Four differential output pairs with selectable pin type: LVDS or

LVPECL. Each output pair is individually selectable for 100MHz

or 125MHz (for PCIe and Ethernet applications).

One differential clock input pair CLK/nCLK can accept the

following differential input levels: LVPECL, LVDS, M-LVDS,

LVHSTL, HCSL

One M-LVDS I/O (MLVDS/nMLVDS)

Output frequency range: 98MHz - 165MHz

Input frequency range: 19.6MHz - 165MHz

VCO range: 490MHz - 660MHz

PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant

External feedback for “zero delay” clock regeneration

RMS phase jitter @ 125MHz (1.875MHz – 20MHz):

0.57ps (typical)

Full 3.3V supply mode

-40°C to 85°C ambient operating temperature

Available in lead-free (RoHS 6) packages

ICS

The ICS8743004I uses very low phase noise FemtoClock™

technology, thus making it ideal for such applications as PCI

Express Generation 1 and 2 as well as for Gigabit Ethernet, Fibre

Channel, and 10 Gigabit Ethernet. It is packaged in a 40-VFQFN

package (6mm x 6mm).

Pin Assignment

PDIV1

PDIV0

nCLK

DDO

DDA

CLK

nQ0

nQ1

OE_MLVDS

MLVDS

nMLVDS

PLL_SEL

FBO_DIV

OE0

OE1

GND

40 39 38 37 36 35 34 33 32 31

11 12 13 14 15 16 17 18 19 20

GND

QDIV0

QDIV1

FBI_DIV0

QDIV2

FBI_DIV1

QDIV3

nFBIN

FBIN

DDO

nQ2

GND

nQ3

FBOUT

nFBOUT

DDO

Q_TYPE

ICS8743004I

40-Lead VFQFN

6mm x 6mm x 0.925mm package body

K Package

Top View

The

Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.

Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.

IDT™ / ICS™

LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 1

ICS8743004DKI REV. A AUGUST 25, 2008

8743004DKILF Related Products

	8743004DKILF	8743004DKILFT
Description	PLL Based Clock Driver, 8743004 Series, 4 True Output(s), 0 Inverted Output(s), 6 X 6 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220, VFQFN-40	PLL Based Clock Driver, 8743004 Series, 4 True Output(s), 0 Inverted Output(s), 6 X 6 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220, VFQFN-40
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	QFN	QFN
package instruction	HVQCCN,	HVQCCN,
Contacts	40	40
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
series	8743004	8743004
Input adjustment	DIFFERENTIAL MUX	DIFFERENTIAL MUX
JESD-30 code	S-XQCC-N40	S-XQCC-N40
JESD-609 code	e3	e3
length	6 mm	6 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Number of functions	1	1
Number of terminals	40	40
Actual output times	4	4
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Output characteristics	OPEN-EMITTER	OPEN-EMITTER
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260
Certification status	Not Qualified	Not Qualified
Maximum seat height	1 mm	1 mm
Maximum supply voltage (Vsup)	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	30	30
width	6 mm	6 mm
minfmax	160 MHz	160 MHz
Base Number Matches	1	1

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