THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
DS 3292 -1
SP8716/8/9
520MHz LOW CURRENT TWO-MODULUS DIVIDERS
SP8716
÷
40/41, SP8718
÷
64/65, SP8719
÷
80/81 are
50mW programmable dividers with a maximum specified
operating frequency of 520MHz over the temperature range
-40
°C
to + 85
°C.
The signal (clock) inputs are biased internally and require
to be capacitor coupled. The output stage is of an unusual low
power design featuring dynamic pull-up, and optimised for
driving CMOS. The 0 to 1 output edge should be used to give
the best loop delay performance.
MODULUS CONTROL UNIT
OUTPUT Vcc
OUTPUT
0V
1
2
3
4
8
Vcc
NO CONNECTION
INPUT
INPUT DECOUPLING
SP
8716/8/9
7
6
5
FEATURES
DC to 520MHz Operation
-40°C to +85°C Temperature Range
Control Inputs and Outputs are CMOS Compatible
Figure : 1 Pin connections - top view
DP8, MP8
QUICK REFERENCE DATA
Supply Voltage 5.0V
±
0.25V
Supply Current 10.5mA typ.
ABSOLUTE MAXIMUM RATINGS
Supply voltage pin 2 or 8):
Storage temperature range:
Max. Junction temperature:
Max. clock I/P voltage:
8V
-55°C to +150°C
+175°C
2.5V p-p
Vcc
8
Vcc
2
7k
SIGNAL
INPUT
6
5
÷P/P + 1
1.5k
1k
300
3 OUTPUT
4
0V
1
MODULUS
CONTROL
INPUT
Figure 2 : Functional diagram
SP8716/8/9
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):]
Supply voltage: Vcc = +4/95 to 5.45V, Temperature: T
amb
= -40°C to +85°C
Value
Characteristics
Max. frequency
Min. frequency (sinewave input)
Power supply current
Output high voltage
Output low voltage
Control input high voltage
Control input low voltage
Control input high current
Control input low current
Clock to output delay
Set-up time
Release time
NOTES
1. Tested at 25°C only
2. Guaranteed but not tested
Symbol
f
max
f
min
I
CC
V
OH
V
OL
V
INH
V
INL
V
INH
VINL
t
p
t
s
t
r
10
10
-0.20
28
3.3
0
(V
cc
- 1.2)
1
8
1.7
0.41
Min.
520
30
11.9
Max.
MHz
MHz
mA
V
V
V
V
mA
mA
ns
ns
ns
Units
Conditions
Input 100-280mV p-p
Input 400-800mV p-p
C
L
= 3pF; pins 2, 8 linked
I
L
= -0.2mA
I
L
= 0.2mA
÷P
÷P
+1
V
INH
= 8V
V
INL
= 0V
C
L
= 10pF
C
L
= 10pF
C
L
= 10pF
Notes
1
2
1
1
1
1
1
1
1
2
2
2
NOTE
The set-up time ts is defined as the minimum time that can elapse between a L
¡
H transition of the control input
and the next L
¡
H clock pulse transition to ensure that the
÷P
mode is obtained.
The release time tr is defined as the minimum time that can elapse between a H
¡
L transition of the control input
and the next L
¡
H clock pulse transition to ensure that the
÷(P
+1) mode is obtain
Figure 3 : Timing diagram
INPUT AMPLITUDE (mV p-p)
1000
800
600
400
200
0
30
100
200
300
400
500
FREQUENCY IN MHz
520mV
GUARANTEED *
OPERATING
WINDOW
280mV
*Tested as
specified in
table of
Electrical
Characteristics
Figure 4 : Typical input characteristics
SP8716/8/9
OPERATING NOTES
1. The inputs are biased internally and coupled to a signal
source with suitable capacitors.
2. If no signal is present the devices will self-oscillate. If this
is undesirable it may be prevented by connecting a 15k
resistor from one input to pin 4 (ground). This will reduce the
sensitivity.
3. The circuits will operate down to DC but slew rate must
be better than 100V/,us.
4. The output stage is of an unusual design and is intended
to interface with CMOS. External pull-up resistors or circuits
must not be used.
5. This device is NOT suitable for driving TTL or its
derivatives.
Vcc
CONTROL
INPUT
1
2
3
OUTPUT
4
8
7
6
5
1n
50
SIGNAL
SOURCE
50
MONITOR
1n
0V
Figure 5: Toggle frequency test circuit
Figure 6 : Typical input impedance
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