8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Table of Contents
Features ......................................................................................................................................................................................................................... 1
DC Electrical Characteristics .......................................................................................................................................................................................... 10
AC Electrical Characteristics ........................................................................................................................................................................................... 11
AC Test Conditions ........................................................................................................................................................................................................ 12
Signal Descriptions ................................................................................................................................................................................................... 23-28
Table 2 — Default Programmable Flag Offsets ................................................................................................................................................................ 14
Table 3 — Status Flags for IDT Standard Mode ............................................................................................................................................................. 17
Table 4 — Status Flags for FWFT Mode ........................................................................................................................................................................ 17
Table 5 — I/O Voltage Level Configuration ..................................................................................................................................................................... 18
Figure 2a. AC Test Load ................................................................................................................................................................................................ 12
Figure 3. Programmable Flag Offset Programming Methods ........................................................................................................................................... 15
Figure 4. Offset Registers Serial Bit Sequence ................................................................................................................................................................ 16
Figure 9. TAP Controller State Diagram ......................................................................................................................................................................... 31
Figure 12. Write Cycle and Full Flag Timing (IDT Standard mode, SDR to SDR, x40 In to x40 Out) ............................................................................... 36
Figure 13. Write Cycle and Full Flag Timing in DDR mode ( IDT Standard mode, DDR to DDR, x40 In to x40 Out) ...................................................... 37
Figure 14. Write Cycle and Full Flag Timing with bus-matching and rate matching (IDT Standard mode, DDR to SDR, x10 In to x20 Out) ..................... 38
Figure 15. Write Cycle and Full Flag Timing with rate matching (IDT Standard mode, SDR to DDR, x40 In to x40 Out) ................................................. 39
Figure 16. Write Timing in FWFT mode (FWFT mode, SDR to SDR, x40 In to x40 Out) ................................................................................................. 40
Figure 17. Write Cycle and First Word Latency Timing in DDR mode (FWFT mode, DDR to DDR, x40 In to x40 Out) .................................................... 41
Figure 18. Read Cycle, Empty Flag & First Word Latency (IDT Standard mode, SDR to SDR, x40 In to x40 Out) .......................................................... 42
Figure 19. Read Cycle, Empty Flag & First Word Latency in DDR mode (IDT Standard mode, DDR to DDR, x40 In to x40 Out) ................................... 43
Figure 20. Read Cycle, Empty Flag & First Word Latency w/ bus-matching and rate-matching (IDT Standard mode, DDR to SDR, x40 In to x20 Out) ... 44
Figure 21. Read Cycle and Empty Flag Timing with bus-matching and rate-matching (IDT Standard mode, SDR to DDR, x10 In to x20 Out) ................ 45
Figure 22. Read Timing at Full Boundary (FWFT mode, SDR to SDR, x40 In to x40 Out) ............................................................................................. 46
Figure 23. Composite Empty Flag (IDT Standard mode, SDR to SDR, x40 In to x40 Out) .............................................................................................. 47
Figure 24. Composite Output Ready Flag (FWFT mode, SDR to SDR, x40 In to x40 Out) ............................................................................................. 47
Figure 25. Composite Full Flag (IDT Standard mode, SDR to SDR, x40 In to x40 Out) .................................................................................................. 48
Figure 26. Composite Input Ready Flag (FWFT mode, SDR to SDR, x40 In to x40 Out) ................................................................................................ 48
Figure 27. Queue Switch at Every Clock Cycle (IDT Standard mode, SDR to SDR, x40 In to x40 Out) .......................................................................... 49
Figure 28. Echo Read Clock and Read Enable Operation (IDT Standard mode, SDR to SDR, x40 In to x40 Out) .......................................................... 50
Figure 29. Echo RCLK and Echo Read Enable Operation (FWFT mode, SDR to SDR, x40 In to x40 Out) .................................................................... 51
Figure 30. Echo Read Clock and Read Enable Operation (IDT Standard mode, DDR to DDR, x10 In to x10 Out) ......................................................... 52
Figure 31. Loading of Programmable Flag Registers (IDT Standard and FWFT modes) ................................................................................................ 53
Figure 32. Reading of Programmable Flag Registers (IDT Standard and FWFT modes) ................................................................................................ 53
Figure 33. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT mode, SDR to SDR, x40 In to x40 Out) .............................. 54
Figure 34. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT mode, SDR to SDR, x40 In to x40 Out) ........................... 54
Figure 35. Power Down Operation ................................................................................................................................................................................ 55
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Talking
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