AD7884AN datasheet, PDF - EEWORLD Datasheet

a

FEATURES

Monolithic Construction

Fast Conversion: 5.3 s

High Throughput: 166 kSPS

Low Power: 250 mW

APPLICATIONS

Automatic Test Equipment

Medical Instrumentation

Industrial Control

Data Acquisition Systems

Robotics

LC

2

MOS

16-Bit, High Speed Sampling ADCs

AD7884/AD7885

FUNCTIONAL BLOCK DIAGRAMS

±3V

IN

F

±3V

IN

S

AGNDS AGNDF AV

DD

AV

SS

V

DD

V

SS

R2

3kΩ

R1

5kΩ

R4 4kΩ

SW2

R6

2kΩ

R5

4kΩ

V

REF–

A2

SW3

16-BIT

ACCURATE

DAC

9

CS

TIMER

CONTROL

RD

9

R3 3kΩ

C1

SW1

A1

AD7884

±5V

IN

S

±5V

IN

F

9-BIT

ADC

9

LATCH

+

16

ALU

O

U

T

P

U

T

D

R

I

V

E

R

S

DB15

16

DB0

GENERAL DESCRIPTION

R7

2kΩ

The AD7884/AD7885 is a 16-bit monolithic analog-to-digital

converter with internal sample-and-hold and a conversion time

of 5.3

µs.

The maximum throughput rate is 166 kSPS. It uses a

two pass flash architecture to achieve this speed. Two input

ranges are available:

±

5 V and

±

3 V. Conversion is initiated by

the

CONVST

signal. The result can be read into a microproces-

sor using the

CS

and

RD

inputs on the device. The AD7884 has

a 16-bit parallel reading structure while the AD7885 has a byte

reading structure. The conversion result is in 2s complement

code.

The AD7884/AD7885 has its own internal oscillator which con-

trols conversion. It runs from

±

5 V supplies and needs a V

REF+

of +3 V.

The AD7884 is available in a 40-pin plastic DIP package and in

a 44-pin PLCC package.

The AD7885 is available in a 28-pin plastic DIP package and

the AD7885A is available in a 44-pin PLCC package.

R8

2kΩ

V

REF+

F V

REF+

S V

INV

V

REF–

GND

CONVST

BUSY

DGND

±3V

IN

AGNDS

AGNDF AV

DD

AV

SS

V

DD

V

SS

±5V

IN

S

±5V

IN

F

R2

3kΩ

R1

5kΩ

R4 4kΩ

R3 3kΩ

C1

SW1

A1

AD7885

SW2

R6

2kΩ

R5

4kΩ

V

REF–

A2

SW3

16-BIT

ACCURATE

DAC

9

9-BIT

ADC

9

LATCH

+

16

ALU

9

O

U

T

P

U

T

D

R

I

V

8

E

R

S

DB7

DB0

CS

TIMER

CONTROL

RD

HBEN

R7

2kΩ

R8

2kΩ

V

REF+

F

V

REF+

S V

INV

V

REF–

GND

CONVST

BUSY

DGND

REV. C

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700

Fax: 617/326-8703

= +5 V 5%, V

SS

= –5 V

= +3 V; AGND = DGND = GND = 0 V; f

SAMPLE

= 166 kHz. All specifications T

MIN

to T

MAX

, unless otherwise noted.)

DD

AD7884/AD7885/AD7885A–SPECIFICATIONS

(V

A

B

Version

1, 2, 3

Versions

1, 2, 3

16

±

0.03

±

2

±

0.05

±

8

±

0.03

±

2

120

84

82

–88

–84

–88

–84

5.3

2.5

166

±

5

±

3

±

4

±

5

2.4

0.8

±

10

4.0

0.4

10

15

+5

–5

35

30

86

325

16

±

0.0075

±

0.03

±

0.05

±

2

±

0.05

±

0.15

±

8

±

0.03

±

0.05

±

2

120

84

82

–88

–84

–88

–84

5.3

2.5

166

±

5

±

3

±

4

±

5

2.4

0.8

±

10

4.0

0.4

10

15

+5

–5

35

30

86

325

Units

Bits

% FSR max

% FSR typ

% FSR max

ppm FSR/°C typ

% FSR typ

% FSR max

ppm FSR/°C typ

% FSR typ

% FSR max

ppm FSR/°C typ

µV

rms typ

dB min

dB typ

dB max

dB typ

dB max

dB typ

µs

max

µs

max

kSPS max

Volts

mA max

V min

V max

µA

max

pF max

V min

V max

µA

max

pF max

V nom

mA max

dB typ

mW max

5%, V

REF

+S

Parameter

DC ACCURACY

Resolution

Minimum Resolution for Which

No Missing Codes Are Guaranteed

Integral Nonlinearity

Positive Gain Error

Gain TC

4

Bipolar Zero Error

Bipolar Zero TC

4

Negative Gain Error

Offset TC

4

Noise

DYNAMIC PERFORMANCE

Signal to (Noise + Distortion) Ratio

Total Harmonic Distortion

Peak Harmonic or Spurious Noise

Intermodulation Distortion (IMD)

2nd Order Terms

3rd Order Terms

CONVERSION TIME

Conversion Time

Acquisition Time

Throughput Rate

ANALOG INPUT

Voltage Range

Input Current

REFERENCE INPUT

Reference Input Current

LOGIC INPUTS

Input High Voltage, V

INH

Input Low Voltage, V

INL

Input Current, I

IN

Input Capacitance, C

IN4

LOGIC OUTPUTS

Output High Voltage, V

OH

Output Low Voltage, V

OL

DB15–DB0

Floating-State Leakage Current

Floating-State Output Capacitance

4

POWER REQUIREMENTS

V

DD

V

SS

I

DD

I

SS

Power Supply Rejection Ratio

∆Gain/∆V

DD

∆Gain/∆V

SS

Power Dissipation

Test Conditions/Comments

Typically 0.003% FSR

AD7885AN/BN: 0.1% typ

AD7885BN: 0.2% max

AD7885AN/BN: 0.1% typ

AD7885BN: 0.2% max

78

µV

rms typical in

±

3 V Input Range

Input Signal:

±

5 V, 1 kHz Sine Wave, Typically 86 dB

Input Signal:

±

5 V, 12 kHz Sine Wave

Input Signal:

±

5 V, 1 kHz Sine Wave

Input Signal:

±

5 V, 12 kHz Sine Wave

Input Signal:

±

5 V, 1 kHz Sine Wave

f

A

= 11.5 kHz, f

B

= 12 kHz, f

SAMPLE

= 166 kHz

f

A

= 11.5 kHz, f

B

= 12 kHz, f

SAMPLE

= 166 kHz

There is an overlap between conversion and acquisition.

V

REF

+ S = +3 V

V

DD

= 5 V

±

5%

V

DD

= 5 V

±

5%

Input Level = 0 V to V

DD

I

SOURCE

= 40

µA

I

SINK

= 1.6 mA

±

5% for Specified Performance

±

5% for Specified Performance

Typically 25 mA

Typically 250 mW

NOTES

1

Temperature ranges are as follows: A, B Versions: –40°C to +85°C.

2

V

IN

=

±

5 V.

3

The AD7885AAP has the same specs as the AD7884AP. The AD7885ABP has the same specs as the AD7884BP.

4

Sample tested to ensure compliance.

Specifications subject to change without notice.

–2–

REV. C

AD7884/AD7885

TIMING CHARACTERISTICS

1, 2

(V

Parameter

t

1

t

2

t

3

t

4

t

5

t

6 2

t

7 3

t

8

t

9

t

10

t

11

t

12

t

13

t

14

Limit at +25 C

(All Versions)

50

100

0

60

0

57

5

50

40

10

25

60

55

50

100

0

60

0

57

5

50

40

80

25

60

70

DD

= +5 V

5%, V

SS

= –5 V

Units

ns min

ns max

ns min

ns max

ns min

ns max

ns min

ns max

5%, AGND = DGND = GND = 0 V. See Figures 2, 3, 4 and 5.)

Conditions/Comments

CONVST

Pulse Width

CONVST

to

BUSY

Low Delay

CS

to

RD

Setup Time

RD

Pulse Width

CS

to

RD

Hold Time

Data Access Time after

RD

Bus Relinquish Time after

RD

New Data Valid before Rising Edge of

BUSY

HBEN to

RD

Setup Time

HBEN to

RD

Hold Time

HBEN Low Pulse Duration

HBEN High Pulse Duration

Propagation Delay from HBEN Falling to Data Valid

Propagation Delay from HBEN Rising to Data Valid

Limit at T

MIN

, T

MAX

(A, B Versions)

NOTES

1

Timing specifications in

bold

print are 100% production tested. All other times are sample tested at +5

°C

to ensure compliance. All input signals are specified

with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

t

6

is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

3

t

7

is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrap-

olated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t

7

, quoted in the Timing Characteristics is the true

bus relinquish time of the part and as such is independent of external bus loading capacitances.

Specifications subject to change without notice.

ORDERING GUIDE

Model

1

AD7884AN

AD7884BN

AD7884AP

AD7884BP

AD7885AN

AD7885BN

AD7885AAP

AD7885ABP

Linearity

Temperature

Range

–40°C to +85°C

Error

(% FSR)

±

0.0075

±

0.0075

±

0.0075

±

0.0075

SNR

(dB)

84

Package

Option

2

N-40A

P-44A

N-28A

P-44A

1.6mA

I

OL

TO OUTPUT PIN

+2.1V

C

L

100pF

200µA

I

OH

NOTES

1

Analog Devices reserves the right to ship cerdip (Q) packages in lieu of plastic

DIP (N) packages.

2

N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC).

Figure 1. Load Circuit for Access Time and Bus Relinquish

Time

REV. C

–3–

AD7884/AD7885

CONVST

t

1

CONVST

t

1

CS

t

2

t

3

RD

t

4

t

5

BUSY

t

CONVERT

t

2

t

CONVERT

BUSY

t

8

t

6

DATA

Hi-Z

DATA

VALID

t

7

Hi-Z

DATA

OLD DATA VALID

NEW DATA VALID

Figure 2. AD7884 Timing Diagram, Using

CS

and

RD

t

1

CONVST

Figure 3. AD7884 Timing Diagram, with

CS

and

RD

Permanently Low

t

9

HBEN

t

10

CS

t

3

RD

t

4

t

5

t

2

BUSY

t

CONVERT

t

7

t

6

Hi-Z

DATA

VALID

DB0–DB7

Hi-Z

DATA

VALID

DB8–DB15

Hi-Z

DATA

Figure 4. AD7885 Timing Diagram, Using

CS

and

RD

CONVST

t

1

t

11

t

12

HBEN

t

2

BUSY

t

CONVERT

t

8

DATA

OLD DATA VALID

(DB8 – DB15)

t

13

NEW DATA VALID

(DB8 – DB15)

t

14

NEW DATA VALID

(DB0 – DB7)

NEW DATA VALID

(DB8 – DB15)

NEW DATA VALID

(DB0 – DB7)

Figure 5. AD7885 Timing Diagram, with

CS

and

RD

Permanently Low

–4–

REV. C

AD7884/AD7885

ABSOLUTE MAXIMUM RATINGS

1

V

DD

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV

DD

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

SS

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V

AV

SS

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to –7 V

AGND Pins to DGND . . . . . . . . . . . . –0.3 V to V

DD

+ 0.3 V

AV

DD

to V

DD2

. . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV

SS

to V

SS2

. . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V

GND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V

DD

+ 0.3 V

V

IN

S, V

IN

F to AGND . . . . . . . . . . V

SS

–0.3 V to V

DD

+ 0.3 V

V

REF+

to AGND . . . . . . . . . . . . . . . V

SS

–0.3 V to V

DD

+ 0.3 V

V

REF–

to AGND . . . . . . . . . . . . . . . V

SS

–0.3 V to V

DD

+ 0.3 V

V

INV

to AGND . . . . . . . . . . . . . . . V

SS

–0.3 V to V

DD

+ 0.3 V

Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V

DD

+ 0.3 V

Digital Outputs to DGND . . . . . . . . . . –0.3 V to V

DD

+ 0.3 V

Operating Temperature Range

Commercial Plastic (A, B Versions) . . . . . –40°C to +85°C

Industrial Cerdip (A, B Versions) . . . . . . . . –40°C to +85°C

Extended Cerdip (T Versions) . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C

Power Dissipation (Any Package) to +75°C . . . . . . . 1000 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C

1

Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those listed in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2

If the AD7884/AD7885 is being powered from separate analog and digital supplies,

AV

SS

should always come up before V

SS

. See Figure 12 for a recommended

protection circuit using Schottky diodes.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although these devices feature proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

PIN CONFIGURATIONS

DIP

±5V

IN

S

±3V

IN

S

±3V

IN

F

V

REF

PLCC

V

REF+

S

V

REF+

F

DB15

DB14

41

V

INV

V

INV

V

REF–

±3V

IN

S

±3V

IN

F

±5V

IN

S

±5V

IN

F

AGNDS

AGNDF

AV

DD

AV

SS

GND

V

SS

V

SS

V

DD

CONVST

CS

RD

V

SS

BUSY

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

V

REF+

S

V

REF+

F

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DGND

V

DD

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

V

REF–

±3V

IN

±5V

IN

S

±5V

IN

F

AGNDS

AGNDF

AV

DD

AV

SS

GND

1

2

3

4

5

6

7

8

9

28 V

INV

27

26

25

24

V

REF+

S

V

REF+

F

DB7

DB6

±5V

IN

F 7

AGNDS 8

AGNDF 9

AV

DD

10

AV

SS

11

NC 12

6

5

4

3

2

NC

1

44

43

42

40

DB13

39

38

37

DB12

DB11

DB10

36 DB9

23 DB5

AD7884

TOP VIEW

(Not to Scale)

35 DB8

34

33

32

NC

DGND

V

DD

AD7885

TOP VIEW

(Not to Scale)

22 DB4

21

20

DGND

DB3

GND 13

GND 14

V

SS

15

V

SS

16

V

DD

17

18

19

20

21

AD7884

TOP VIEW

(Not to Scale)

33

32

31

30

29

28

27

26

25

24

23

22

21

31 DB7

30 DB6

29 DB5

22

23

24

25

26

27

28

V

SS

10

V

DD

11

CONVST 12

CS 13

RD 14

19 DB2

18

DB1

CONVST

V

SS

CS

RD

NC

DB0

DB1

BUSY

DB2

DB3

NC

17 DB0

16 BUSY

15 HBEN

NC = NO CONNECT

V

REF+

S

±5V

IN

S

±3V

IN

F

±3V

IN

S

V

REF+

F

V

REF

V

INV

NC

6

5

4

3

2

1

NC

44

43

42

41 40

±5V

IN

F

AGNDS

AGNDF

NC

39 DB7

38 DB6

37 NC

36 DB5

35 DB4

34 NC

33 DGND

32 V

DD

31 DB3

30 DB2

29 DB1

28

7

8

9

AV

DD

10

AV

SS

11

AD7885A

TOP VIEW

(Not to Scale)

NC 12

GND 13

GND 14

V

SS

15

V

SS

16

V

DD

17

18

19

20

21

22

23

24

25

26

27

CONVST

RD

NC

HBEN

BUSY

NC = NO CONNECT

REV. C

–5–

DB0

CS

DB4

AD7884AN

AD7884AN Overview

Preview

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