Changes to Ordering Guide .......................................................... 20
7/04—Revision 0: Initial Version
AD7940
SPECIFICATIONS
1
V
DD
= 2.50 V to 5.5 V, f
SCLK
= 2.5 MHz, f
SAMPLE
= 100 kSPS, unless otherwise noted; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)
2
Total Harmonic Distortion (THD)
2
Peak Harmonic or Spurious Noise (SFDR)
2
Intermodulation Distortion (IMD)
2
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
2
Offset Error
2
Gain Error
2
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN2, 3
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
2, 3
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode
B Version
1
81
−98
−95
−94
−100
20
30
7
2
14
13
±1
±2
±6
±8
0 to V
DD
±0.3
30
2.4
0.4
0.8
±0.3
10
Unit
dB min
dB typ
dB typ
dB typ
dB typ
ns max
ps typ
MHz typ
MHz typ
Bits min
Bits min
LSB max
LSB max
LSB max
LSB max
V
µA max
pF typ
V min
V max
V max
µA max
pF max
Test Conditions/Comments
f
IN
= 10 kHz sine wave
@ −3 dB
@ −0.1 dB
V
DD
= 2.5 V to 4.096 V
V
DD
> 4.096 V
V
DD
= 2.5 V to 4.096 V
V
DD
> 4.096 V
V
DD
= 3 V
V
DD
= 5 V
Typically 10 nA, V
IN
= 0 V or V
DD
V
DD
– 0.2
V min
0.4
V max
±0.3
µA max
10
pF max
Straight (Natural) Binary
8
500
400
100
2.50/5.5
5.2
2
4.8
1.9
0.5
0.3
µs max
ns max
ns max
kSPS max
V min/V max
mA max
mA max
mA max
mA max
µA max
µA max
Rev. A | Page 3 of 20
I
SOURCE
= 200 µA; V
DD
= 2.50 V to 5.25 V
I
SINK
= 200 µA
16 SCLK cycles
Full-scale step input
Sine wave input ≤ 10 kHz
See the Serial Interface section
Digital I/P
S
= 0 V or V
DD
V
DD
= 5.5 V; SCLK on or off
V
DD
= 3.6 V; SCLK on or off
V
DD
= 5.5 V; f
SAMPLE
= 100 kSPS; 3.3 mA typ
V
DD
= 3.6 V; f
SAMPLE
= 100 kSPS; 1.29 mA typ
SCLK on or off. V
DD
= 5.5 V
SCLK on or off. V
DD
= 3.6 V
AD7940
Parameter
Power Dissipation
4
Normal Mode (Operational)
Full Power-Down
1
2
B Version
1
26.4
6.84
2.5
1.08
Unit
mW max
mW max
µW max
µW max
Test Conditions/Comments
V
DD
= 5.5 V
V
DD
= 5.5 V; f
SAMPLE
= 100 kSPS
V
DD
= 3.6 V; f
SAMPLE
= 100 kSPS
V
DD
= 5.5 V
V
DD
= 3.6 V
Temperature range for B Version is –40°C to +85°C.
See the Terminology section.
3
Sample tested at initial release to ensure compliance.
4
See the Power vs. Throughput Rate section.
Rev. A | Page 4 of 20
AD7940
TIMING SPECIFICATIONS
Sample tested at initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from
a voltage level of 1.6 V.
V
DD
= 2.50 V to 5.5 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
f
SCLK 1
t
CONVERT
t
QUIET
t
1
t
2
t
3 2
t
4 2
t
5
t
6
t
7
t
8 3
t
POWER-UP 4
1
2
Limit at T
MIN
, T
MAX
3V
5V
250
250
2.5
2.5
16 × t
SCLK
16 × t
SCLK
50
50
10
10
48
120
0.4 t
SCLK
0.4 t
SCLK
10
45
1
10
10
35
80
0.4 t
SCLK
0.4 t
SCLK
10
35
1
Unit
kHz min
MHz max
min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
µs typ
Description
Minimum quiet time required between bus relinquish and start of
next conversion
Minimum CS pulse width
CS to SCLK setup time
Delay from CS until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to SDATA high impedance
Power up time from full power-down
Mark/space ratio for the SCLK input is 40/60 to 60/40.
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
3
t
8
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
4
See the Power vs. Throughput Rate section.
200µA
I
OL
TO OUTPUT
PIN
1.6V
C
L
50pF
200µA
I
OH
03305-0-002
Figure 2. Load Circuit for Digital Output Timing Specification
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